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1998 microchip technology inc. preliminary ds30235g-page 1 devices included in this data sheet: referred to collectively as pic16c62x . pic16c620 pic16c620a pic16c621 pic16c621a pic16c622 pic16c622a pic16cr620a high performance risc cpu: only 35 instructions to learn all single-cycle instructions (200 ns), except for program branches which are two-cycle operating speed: - dc - 20 mhz clock input - dc - 200 ns instruction cycle interrupt capability 16 special function hardware registers 8-level deep hardware stack direct, indirect and relative addressing modes peripheral features: 13 i/o pins with individual direction control high current sink/source for direct led drive analog comparator module with: - two analog comparators - programmable on-chip voltage reference (v ref ) module - programmable input multiplexing from device inputs and internal voltage reference - comparator outputs can be output signals timer0: 8-bit timer/counter with 8-bit programmable prescaler special microcontroller features: power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) brown-out reset watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation device program memory data memory pic16c620 512 80 pic16c620a 512 96 pic16cr620a 512 96 pic16c621 1k 80 pic16c621a 1k 96 pic16c622 2k 128 pic16c622a 2k 128 pin diagrams special microcontroller features (contd) programmable code protection power saving sleep mode selectable oscillator options serial in-circuit programming (via two pins) four user programmable id locations cmos technology: low-power, high-speed cmos eprom technol- ogy fully static design wide operating voltage range - pic16c62x - 2.5v to 6.0v - pic16c62xa - 2.5v to 5.5v - pic16cr620a - 2.0v to 5.5v commercial, industrial and extended tempera- ture range low power consumption - < 2.0 ma @ 5.0v, 4.0 mhz - 15 m a typical @ 3.0v, 32 khz - < 1.0 m a typical standby current @ 3.0v ra1/an1 ra0/an0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2/an2/v ref ra3/an3 mclr/ v pp v ss rb0/int rb1 rb2 rb3 ra4/t0cki pic16c62x ra1/an1 ra0/an0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2/an2/v ref ra3/an3 mclr/ v pp v ss v ss rb0/int rb1 rb2 ra4/t0cki rb3 rb3 v dd pdip, soic, windowed cerdip ssop 2 3 4 5 6 7 8 9 10 ? 2 3 4 5 6 7 8 9 ? 19 18 16 15 14 13 12 11 17 18 17 15 14 13 12 11 10 16 20 pic16c62x eprom-based 8-bit cmos microcontroller pic16c62x
pic16c62x ds30235g -page 2 preliminary 1998 microchip technology inc. de vice diff erences note 1: if y ou change from this de vice to another de vice , please v er ify oscillator char acter istics in y our application. de vice v olta g e rang e oscillator pr ocess t ec hnology (micr ons) pic16c620 2.5 - 6.0 see note 1 0.9 pic16c621 2.5 - 6.0 see note 1 0.9 pic16c622 2.5 - 6.0 see note 1 0.9 pic16c620a 2.5 - 5.5 see note 1 0.7 pic16cr620a 2.0 - 5.5 see note 1 0.7 pic16c621a 2.5 - 5.5 see note 1 0.7 pic16c622a 2.5 - 5.5 see note 1 0.7
1998 microchip technology inc. preliminary ds30235g -page 3 pic16c62x t ab le of contents 1.0 general description ............................................................................................................................... ....................................... 5 2.0 pic16c62x d evice varieties ............................................................................................................................... ........................ 7 3.0 architectural overview ............................................................................................................................... .................................. 9 4.0 memory organization ............................................................................................................................... ................................. 13 5.0 i/o ports ............................................................................................................................... ..................................................... 25 6.0 timer0 module ............................................................................................................................... ........................................... 31 7.0 comparator module ............................................................................................................................... .................................... 37 8.0 voltage reference module ............................................................................................................................... ......................... 43 9.0 special features of the cpu ............................................................................................................................... ...................... 45 10.0 instruction set summary ............................................................................................................................... ............................ 61 11.0 development support ............................................................................................................................... ................................. 73 12.0 electrical specifications ............................................................................................................................... .............................. 79 13.0 device characterization information ............................................................................................................................... .......... 93 14.0 packaging information ............................................................................................................................... ................................ 95 appendix a: enhancements ............................................................................................................................... ........................... 101 appendix b: compatibility ............................................................................................................................... .............................. 101 appendix c: what? new ............................................................................................................................... ................................ 102 appendix d: what? changed ............................................................................................................................... ........................ 102 index ............................................................................................................................... ................................................................... 103 pic16c62x product identification system ............................................................................................................................... ......... 107 t o our v alued customers most current data sheet t o obtain the most up-to-date v ersion of this data sheet, please chec k our w or ldwide w eb site at: http://www .microchip .com y ou can deter mine the v ersion of a data sheet b y e xamining its liter ature n umber f ound on the bottom outside cor ner of an y page . the last char acter of the liter ature n umber is the v ersion n umber . e .g., ds30000a is v ersion a of document ds30000. errata an err ata sheet ma y e xist f or current de vices , descr ibing minor oper ational diff erences (from the data sheet) and recommended w or karounds . as de vice/documentation issues become kno wn to us , w e will pub lish an err ata sheet. the err ata will specify the re vi- sion of silicon and re vision of document to which it applies . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please chec k with one of the f ollo wing: microchip s w or ldwide w eb site; http://www .microchip .com y our local microchip sales of ce (see last page) the microchip cor por ate liter ature center ; u .s . f ax: (602) 786-7277 when contacting a sales of ce or the liter ature center , please specify which de vice , re vision of silicon and data sheet (include lit- er ature n umber) y ou are using. corrections to this data sheet w e constantly str iv e to impro v e the quality of all our products and documentation. w e ha v e spent a g reat deal of time to ensure that this document is correct. ho w e v er , w e realiz e that w e ma y ha v e missed a f e w things . if y ou nd an y inf or mation that is missing or appears in error , please: fill out and mail in the reader response f or m in the bac k of this data sheet. e-mail us at w ebmaster@microchip .com. w e appreciate y our assistance in making this a better document.
pic16c62x ds30235g -page 4 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds30235g -page 5 pic16c62x 1.0 general description the pic16c62x are 18 and 20 pin r om/ epr om-based members of the v ersatile picmi- cro f amily of lo w-cost, high -perf or mance , cmos , fully-static , 8-bit microcontrollers . all pic micro m icrocontrollers emplo y an adv anced risc architecture . the pic16c62x h a v e enhanced core f eatures , eight-le v el deep stac k, and m ultiple inter- nal and e xter nal interr upt sources . the separ ate instr uction and data b uses of the har v ard architecture allo w a 14-bit wide instr uction w ord with the separ ate 8-bit wide data. the tw o-stage instr uction pipeline allo ws all instr uctions to e x ecute in a single-cycle , e xcept f or prog r am br anches (which require tw o cycles). a total of 35 instr uctions (reduced instr uction set) are a v ailab le . additionally , a large register set giv es some of the architectur al inno v ations used to achie v e a v er y high perf or mance . pic16c62x m icrocontrollers typically achie v e a 2:1 code compression and a 4:1 speed impro v ement o v er other 8-bit microcontrollers in their c lass . the pic16c620 a , pic16c621 a and pic16cr620a ha v e 96 b ytes of ram. the pic 16c622 (a) ha s 1 28 b ytes of ram. each de vice has 13 i/o pins and an 8-bit timer/counter with an 8-bit prog r ammab le prescaler . in addition, the pic16c62x add s t w o analog compar ators with a prog r ammab le on-chip v oltage ref erence mod- ule . the compar ator module is ideally suited f or appli- cations requir ing a lo w-cost analog interf ace (e .g., batter y chargers , threshold detectors , white goods controllers , etc). pic16c62x de vices ha v e special f eatures to reduce e xter nal components , thus reducing system c ost, enhancing system reliability and reducing po w er con- sumption. there are f our oscillator options , of which the single pin rc oscillator pro vides a lo w-cost solution, the lp oscillator minimiz es po w er consumption, xt is a standard cr ystal, and the hs is f or high speed cr ystals . the sleep (po w er-do wn) mode off ers po w er sa ving s . the user can w ak e up the chip from sleep through se v er al e xter nal and inter nal interr upts and reset. a highly reliab le w atchdog timer with its o wn on-chip rc oscillator pro vides protection against softw are loc k- up . a uv -er asab le cerdip-pac kaged v ersion is ideal f or code de v elopment while the cost-eff ectiv e one-time prog r ammab le (o tp) v ersion is suitab le f or production in an y v olume . t ab le 1-1 sho ws the f eatures of the pic16c62x mid-r ange microcontroller f am ilies . a simpli ed b loc k diag r am of the pic16c62x is sho wn in figure 3-1 . the pic16c62x ser ies t perf ectly in applications r anging from batter y chargers to lo w-po w er remote sensors . the epr om technology mak es customization of application prog r ams (detection le v els , pulse gener- ation, timers , etc.) e xtremely f ast and con v enient. the small f ootpr int pac kages mak e this microcontroller ser ies perf ect f or all applications with space limitations . lo w-cost, lo w-po w er , high- perf or mance , ease of use and i/o e xibility mak e the pic16c62x v er y v ersatile . 1.1 f amil y and upwar d compatibility those users f amiliar with the pic16c5x f amily of microcontrollers will realiz e that this is an enhanced v ersion of the pic16c5x architecture . please ref er to appendix a f or a detailed list of enhancements . code wr itten f or the pic16c5x can be easily por ted to pic16c62x f amily of de vices (appendix b) . the pic16c62x f amily lls the niche f or users w anting to mig r ate up from the pic16c5x f amily and not needing v ar ious per ipher al f eatures of other members of the pic16xx mid-r ange microcontroller f amily . 1.2 de velopment suppor t the pic16c62x f amily is suppor ted b y a full-f eatured macro assemb ler , a softw are sim ulator , an in-circuit em ulator , a lo w-cost de v elopment prog r ammer and a full-f eatured prog r ammer . a ? compiler and fuzzy logic suppor t tools are also a v ailab le .
pic16c62x ds30235g -page 6 preliminary 1998 microchip technology inc. t ab le 1-1: pic16c62x f amil y of de vices pic16c620 pic16c620a pic16cr620a pic16c621 pic16c621a pic16c622 pic16c622a clock maximum frequency of operation (mhz) 20 20 20 20 20 20 20 memory eprom program memory (x14 words) 512 512 512 1k 1k 2k 2k data memory (bytes) 80 96 96 80 96 128 128 peripherals timer module(s) tmr0 tmr0 tmro tmr0 tmr0 tmr0 tmr0 comparators(s) 2 2 2 2 2 2 2 internal reference voltage yes yes yes yes yes yes yes features interrupt sources 4 4 4 4 4 4 4 i/o pins 13 13 13 13 13 13 13 voltage range (volts) 2.5-6.0 3.0-5.5 2.5-5.5 2.5-6.0 3.0-5.5 2.5-6.0 3.0-5.5 brown-out reset yes yes yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic micro f amily de vices ha v e p o w er-on reset, selectab le w atchdog timer , selectab le code protect and high i/o current capability . all pic16c62x f amily de vices use ser ial prog r amming with cloc k pin rb6 and data pin rb7.
1998 microchip technology inc. preliminary ds30235g -page 7 pic16c62x 2.0 pic16c62x d e vice v arieties a v ar iety of frequency r anges and pac kaging options are a v ailab le . depending on application and production requirements the proper de vice option can be selected using the inf or mation in the pic16c62x product identi cation system section at the end of this data sheet. when placing orders , please use this page of the data sheet to specify the correct par t n umber . 2.1 uv erasab le de vices the uv er asab le v ersion, off ered in cerdip pac kage is optimal f or prototype de v elopment and pilot prog r ams . this v ersion can be er ased and reprog r ammed to an y of the oscillator modes . microchip's picst ar t and pr o ma te prog r ammers both suppor t prog r amming of the pic16c62x . 2.2 one-time-pr ogrammab le (o tp) de vices the a v ailability of o tp de vices is especially useful f or customers who need the e xibility f or frequent code updates and small v olume applications . in addition to the prog r am memor y , the con gur ation bits m ust also be prog r ammed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip off ers a qtp prog r amming ser vice f or f actor y production orders . this ser vice is made a v ailab le f or users who chose not to prog r am a medium to high quantity of units and whose code patter ns ha v e stabiliz ed. the de vices are identical to the o tp de vices b ut with all epr om locations and con gur ation o ptions already prog r ammed b y the f actor y . cer tain code and prototype v er i cation procedures apply bef ore production shipments are a v ailab le . please contact y our microchip t echnology sales of ce f or more details . 2.4 serializ ed quic k-t urnar ound-pr oduction (sqtp sm ) de vices microchip off ers a unique prog r amming ser vice where a f e w user-de ned locations in each de vice are prog r ammed with diff erent ser ial n umbers . the ser ial n umbers ma y be r andom, pseudo-r andom or sequential. ser ial prog r amming allo ws each de vice to ha v e a unique n umber which can ser v e as an entr y-code , pass w ord or id n umber .
pic16c62x ds30235g -page 8 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds30235g -page 9 pic16c62x 3.0 ar c hitectural over vie w the high perf or mance of the pic16c62x f amily can be attr ib uted to a n umber of architectur al f eatures commonly f ound in risc microprocessors . t o begin with, the pic16c62x uses a har v ard architecture , in which, prog r am and data are accessed from separ ate memor ies using separ ate b usses . this impro v es bandwidth o v er tr aditional v on neumann architecture where prog r am and data are f etched from the same memor y . separ ating prog r am and data memor y fur ther allo ws instr uctions to be siz ed diff erently than 8-bit wide data w ord. instr uction opcodes are 14-bit s wide making it possib le to ha v e all single w ord instr uctions . a 14-bit wide prog r am memor y access b us f etches a 14-bit instr uction in a single cycle . a tw o-stage pipeline o v er laps f etch and e x ecution of instr uctions . consequently , all instr uctions ( 35 ) e x ecute in a sin- gl e -cycle (200 ns @ 20 mhz) e xcept f or prog r am br anches . the pic16c620 a and pic16cr620a address 512 x 14 on-chip prog r am memor y . t he pic16c621(a) addresses 1k x 14 prog r am memor y . the pic16c622(a) addresses 2k x 14 prog r am memor y . all prog r am memor y is inter nal. the pic16c62x can directly or indirectly address its register les or data memor y . all special function registers including the prog r am counter are mapped in the data memor y . the pic16c62x ha v e an or thogonal (symmetr ical) instr uction set that mak es it possib le to carr y out an y oper ation on an y register using an y addressing mode . this symmetr ical nature and lac k of ?pecial optimal situations mak e prog r amming with the pic16c62x simple y et ef cient. in addition, the lear ning cur v e is reduced signi cantly . the pic16c62x de vices contain an 8-bit alu and w or king register . the alu is a gener al pur pose ar ithmetic unit. it perf or ms ar ithmetic and boolean functions betw een data in the w or king register and an y register le . the alu is 8-bit wide and capab le of addition, subtr action, shift and logical oper ations . unless otherwise mentioned, ar ithmetic oper ations are tw o's complement in nature . in tw o-oper and instr uctions , typically one oper and is the w or king register (w register). the other oper and is a le register or an immediate constant. in single oper and instr uctions , the oper and is either the w register or a le register . the w register is an 8-bit w or king register used f or alu oper ations . it is not an addressab le register . depending on the instr uction e x ecuted, the alu ma y aff ect the v alues of the carr y (c), digit carr y (dc), and zero (z) bits in the st a tus register . the c and dc bits oper ate as a bo rro w and di git bo rro w out bit, respectiv ely , bit in subtr action. see the sublw and subwf instr uctions f or e xamples . a simpli ed b loc k diag r am is sho wn in figure 3-1 , with a descr iption of the de vice pins in t ab le 3-1 .
pic16c62x ds30235g -page 10 preliminary 1998 microchip technology inc. figure 3-1: bloc k dia gram epr om prog r am memor y 13 data bus 8 14 prog r am bus instr uction reg prog r am counter 8 le v el stac k (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg st a tus reg mux alu w reg p o w er-up timer oscillator star t-up timer p o w er-on reset w atchdog timer instr uction decode & control timing gener ation osc1/clkin osc2/clk out mclr v dd , v ss v oltage bro wn-out reset note 1: higher order bits are from the st a tus register . de vice pr ogram memor y data memor y (ram) pic16c620 pic16c620a pic16cr620a pic16c621 pic16c621a pic16c622 pic16c622a 512 x 14 512 x 14 512 x 14 1k x 14 1k x 14 2k x 14 2k x 14 80 x 8 96 x 8 96 x 8 80 x 8 96 x 8 128 x 8 128 x 8 8 3 tmr0 i/o p or ts por tb compar ator ra3/an3 ra2/an2/ v ref ra 1 /an1 ra0/an0 ref erence ra4/t0cki + - + -
1998 microchip technology inc. preliminary ds30235g -page 11 pic16c62x t ab le 3-1: pic16c62x pinout description name dip/ soic pin # ssop pin # i/o/p t ype buff er t ype description osc1/clkin 16 18 i st/cmos oscillator cr ystal input/e xter nal cloc k source input. osc2/clk out 15 17 o oscillator cr ystal output. connects to cr ystal or resonator in cr ystal oscillator mode . in rc mode , osc2 pin outputs clk out which has 1/4 the frequency of osc1, and denotes the instr uction cycle r ate . mclr / v pp 4 4 i/p st master clear (reset) input/prog r amming v oltage input. this pin is an activ e lo w reset to the de vice . por t a is a bi-directional i/o por t. ra0/an0 17 19 i/o st analog compar ator input ra1/an1 18 20 i/o st analog compar ator input ra2/an2/v ref 1 1 i/o st analog compar ator input or v ref output ra3/an3 2 2 i/o st analog compar ator input /output ra4/t0cki 3 3 i/o st can b e selected to be the cloc k input to the timer0 timer/counter or a compar ator output. output is open dr ain type . por tb is a bi-directional i/o por t. por tb can be softw are prog r ammed f or inter nal w eak pull-up on all inputs . rb0/int 6 7 i/o ttl/st (1) rb0/int can also be selected as an e xter nal interr upt pin. rb1 7 8 i/o ttl rb2 8 9 i/o ttl rb3 9 10 i/o ttl rb4 10 11 i/o ttl interr upt on change pin. rb5 11 12 i/o ttl interr upt on change pin. rb6 12 13 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming cloc k. rb7 13 14 i/o ttl/st (2) interr upt on change pin. ser ial prog r amming data. v ss 5 5,6 p ground ref erence f or logic and i/o pins . v dd 14 15,16 p p ositiv e supply f or logic and i/o pins . legend: o = output i/o = input/output p = po w er ?= not used i = input st = schmitt t r igger input ttl = ttl input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. note 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode .
pic16c62x ds30235g -page 12 preliminary 1998 microchip technology inc. 3.1 cloc king sc heme/instruction cyc le the cloc k input ( o sc1 /clkin pin ) is inter nally divided b y f our to gener ate f our non-o v er lapping quadr ature cloc ks namely q1, q2, q3 and q4. inter nally , the prog r am counter (pc) is incremented e v er y q1, the instr uction is f etched from the prog r am memor y and latched into the instr uction register in q4. the instr uction is decoded and e x ecuted dur ing the f ollo wing q1 through q4. the cloc ks and instr uction e x ecution o w is sho wn in figure 3-2 . 3.2 instruction flo w/pipelining an ?nstr uction cycle consists of f our q cycles (q1, q2, q3 and q4). the instr uction f etch and e x ecute are pipelined such that f etch tak es one instr uction cycle while decode and e x ecute tak es another instr uction cycle . ho w e v er , due to the pipelining, each instr uction eff ectiv ely e x ecutes in one cycle . if an instr uction causes the prog r am counter to change (e .g., go t o ) then tw o cycles are required to complete the instr uction ( example 3-1 ). a f etch cycle begins with the prog r am counter (pc) incrementing in q1. in the e x ecution cycle , the f etched instr uction is latched into the ?nstr uction register (ir) in cycle q1. this instr uction is then decoded and e x ecuted dur ing the q2, q3, and q4 cycles . data memor y is read dur ing q2 (oper and read) and wr itten dur ing q4 (destination wr ite). figure 3-2: cloc k /instruction cyc le example 3-1: instruction pipeline flo w q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clk out (rc mode) pc pc+1 pc+2 f etch inst (pc) ex ecute inst (pc-1) f etch inst (pc+1) ex ecute inst (pc) f etch inst (pc+2) ex ecute inst (pc+1) inter nal phase cloc k all instr uctions are single cycle , e xcept f or an y prog r am br anches . these tak e tw o cycles since the f etch instr uction is ushed from the pipeline while the ne w instr uction is being f etched and then e x ecuted. 1. movlw 55h f etch 1 ex ecute 1 2. movwf portb f etch 2 ex ecute 2 3. call sub_1 f etch 3 ex ecute 3 4. bsf porta, bit3 f etch 4 flush f etch sub_1 ex ecute sub_1
1998 microchip technology inc. preliminary ds30235g -page 13 pic16c62x 4.0 memor y or ganization 4.1 pr ogram memor y or ganization the pic16c62x has a 13-bit prog r am counter capab le of addressing an 8k x 14 prog r am memor y space . only the rst 512 x 14 (0000h - 01ffh) f or the pic16c620 (a) and pic16cr620 , 1k x 14 (0000h - 03ffh) f or the pic16c621 (a) and 2 k x 14 (0000h - 07ffh) f or the pic16c622 (a) are ph ysically imple- mented. accessing a location abo v e these boundar ies will cause a wr ap-around within the rst 512 x 14 space (pic16c (r) 620 (a) ) or 1k x 14 space (pic16c621 ( a) ) or 2k x 14 space (pic16c622 (a) ). the reset v ector is at 0000h and the interr upt v ector is at 0004h ( figure 4-1 , figure 4-2 , figure 4-3 ) . figure 4-1: pr ogram memor y map and stac k f or the pic16c620/pic16c620a/ pic16cr620a pc<12:0> 13 000h 0004 0005 01ffh 0200h 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw stac k le v el 2 figure 4-2: pr ogram memor y map and stac k f or the pic16c621/pic16c621a figure 4-3: pr ogram memor y map and stac k f or the pic16c622/pic16c622a pc<12:0> 13 000h 0004 0005 03ffh 0400h 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw stac k le v el 2 pc<12:0> 13 000h 0004 0005 07ffh 0800h 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw stac k le v el 2
pic16c62x ds30235g -page 14 preliminary 1998 microchip technology inc. 4.2 data memor y or ganization the data memor y ( figure 4-4 , figure 4-5 , figure 4-6 and figure 4-7 ) is par titioned into tw o banks which contain the gener al pur pose registers and the special function regis- ters . bank 0 is selected when the rp0 bit is cleared. b a nk 1 is selected when the rp0 bit ( st a tu s <5> ) is set. the special function registers are located in the rst 32 loca- tions of each bank. register locations 20- 7 fh (bank0) on the pic16c620 a/cr620a/621a and 2 0- 7 fh (bank0) and a0- b fh (bank1) on the pic16c622 and pic16c622a are gener al pur pose registers implemented as static ram. some special pur pose registers are mapped in bank 1. addresses f0h-ffh of bank1 are implemented as common r am and mapped bac k to addresses 70h-7fh in bank0 on the pic16c620a/cr620a/621a/622a. 4.2.1 gener al pur pose register file the register le is organiz ed as 80 x 8 in the pic16c620/ 621 , 96 x 8 in the pic16c620a/621a/cr620a and 128 x 8 in the pic16c622 (a) . each is accessed either directly or indi- rectly through the f ile s elect re gister fsr ( section 4.4 ).
1998 microchip technology inc. preliminary ds30235g -page 15 pic16c62x figure 4-4: data memor y map f or the pic16c620/621 indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon pir1 cmcon indf (1) option pcl st a tus fsr trisa trisb pcla th intcon pie1 pcon vrcon 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register 7f h ff h bank 0 bank 1 file address 6fh 70h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address figure 4-5: data memor y map f or the pic16c622 indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon pir1 cmcon indf (1) option pcl st a tus fsr trisa trisb pcla th intcon pie1 pcon vrcon 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register 7f h ff h bank 0 bank 1 file address bfh c0h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address gener al pur pose register
pic16c62x ds30235g -page 16 preliminary 1998 microchip technology inc. figure 4-6: data memor y map f or the pic16c620a/ cr620a/621a indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon pir1 cmcon indf (1) option pcl st a tus fsr trisa trisb pcla th intcon pie1 pcon vrcon 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register 7f h ff h bank 0 bank 1 file address 6fh 70h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address accesses 70h-7fh f0h figure 4-7: data memor y map f or the pic16c622a indf (1) tmr0 pcl st a tus fsr por t a por tb pcla th intcon pir1 cmcon indf (1) option pcl st a tus fsr trisa trisb pcla th intcon pie1 pcon vrcon 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register 7f h ff h bank 0 bank 1 file address bfh c0h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address gener al pur pose register accesses 70h-7fh f0h 6fh 70h
1998 microchip technology inc. preliminary ds30235g -page 17 pic16c62x 4.2.2 special function registers the special function registers are registers used b y the cpu and p er ipher al functions f or controlling the desired oper ation of the de vice ( t ab le 4-1 ). these registers are static ram. the special registers can be classi ed into tw o sets (core and per ipher al). the special function registers associated with the ?ore functions are descr ibed in this section. those related to the oper ation of the per ipher al f eatures are descr ibed in the section of that per ipher al f eature . t ab le 4-1: special register s f or the pic16c62x ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por reset v alue on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) xxxx xx x x xxxx xxxx 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 02h pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 03h st a tus irp (2) rp1 (2) rp0 t o pd z dc c 0001 1xxx 000q quuu 04h fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 05h por t a ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 06h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h unimplemented 08h unimplemented 09h unimplemented 0ah pcla th wr ite b uff er f or upper 5 bits of prog r am counter ---0 0000 ---0 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 cmif -0-- ---- -0-- ---- 0dh-1eh unimplemented 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 bank 1 80h ind f addressing this location uses contents of fsr to address data memor y (not a ph ysical register) xxxx x x xx xxxx xxxx 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 83h st a tus irp (2) rp1 (2) rp0 t o pd z dc c 0001 1xxx 000q quuu 84h fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 87h unimplemented 88h unimplemented 89h unimplemented 8ah pcla th wr ite b uff er f or upper 5 bits of prog r am counter ---0 0000 ---0 0000 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 cmie -0-- ---- -0-- ---- 8dh unimplemented 8eh pcon por bor ---- --0x ---- --uq 8fh-9eh unimplemented 9fh vrcon vren vr oe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend : = unimplemented locations read as ? , u = unchanged, x = unkno wn, q = v alue depends on condition , shaded = unimplemented note 1: other (non po w er-up) resets include mclr reset, bro wn-out r e set and w atchdog timer reset dur ing nor mal oper ation. note 2: irp & rpi bits are reser v ed, alw a ys maintain these bits clear .
pic16c62x ds30235g -page 18 preliminary 1998 microchip technology inc. 4.2.2.1 status register the st a tus register , sho wn in figure 4-8, contains the ar ithmetic status of the alu , the reset status and the bank select bits f or data memor y . the st a tus register can be the destination f or an y instr uction, lik e an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper-three bits and set the z bit. this lea v es the status register as 000uu1uu (where u = unchanged). it is recommended, theref ore , that only bcf, bsf, swapf and movwf instr uctions are used to alter the st a tus register because these instr uctions do not aff ect an y status bit. f or other instr uctions , not aff ecting an y status bits , see the ?nstr uction set summar y? note 1: the irp and rp1 bits (st a tus<7:6>) are not used b y the pic16c62x and should be prog r ammed as ?'. use of these bits as gener al pur pose r/w bits is no t recommended, since this ma y aff ect upw ard compatibility with future products . note 2: the c and dc bits oper ate as a borro w and digit borro w out bit, respectiv ely , in subtr action. see the sublw and subwf instr uctions f or e xamples . figure 4-8: st a tus register (ad dress 03h or 83h) reser v ed reser v ed r/w -0 r-1 r-1 r/w -x r/w -x r/w -x irp rp1 rp0 t o pd z dc c r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset -x = unkno wn at por reset bit7 bit0 bit 7: irp : register bank sele ct bit (used f or indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ff h ) the irp bit is reser v ed on the pic16c62x , alw a y s maintain this bit clear . bit 6 -5: rp1:rp0 : register bank sel ect bits (used f or direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 b ytes . the rp1 bit is reser v ed on the pic16c62x , al w a ys maintain this bit clear . bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z : zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc : digit carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions)(f or borro w the polar ity is re v ersed) 1 = a carr y-out from the 4th lo w order bit of the result occurred 0 = no carr y-out from the 4th lo w order bit of the resul t bit 0 : c : carr y/ borro w bit ( a ddwf , a ddlw , s ublw, s ubwf i nstr uctions) 1 = a carr y-out from the most signi cant bit of the result occurre d 0 = no carr y-out from the most signi cant bit of the result occurred note: f o r borro w the polar ity is re v ersed. a subtr action is e x ecuted b y adding the tw o s complement of the second oper and. f or rotate ( rrf , rlf ) instr uctions , this bit is loaded with either the high or lo w order bit of the source register .
1998 microchip technology inc. preliminary ds30235g -page 19 pic16c62x 4.2.2.2 option register the option register is a readab le and wr itab le register which contains v ar ious control bits to con gure the tmr0/wdt prescaler , the e xter nal rb0/int interr upt, tmr0, and the w eak pull-ups on por tb . note: t o achie v e a 1:1 prescaler assignment f or tmr0, assign the prescaler to the wdt (psa = 1). figure 4-9: option register (ad dress 81h) r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readab le bit w = wr itab le bi t - n = v alue at por reset bit7 bit0 bit 7: rbpu : por tb pull-up ena b le bit 1 = por tb pull-ups are disab led 0 = por tb pull-ups are enab led b y individual por t latch v alues bit 6: intedg : interr upt edge sele ct bit 1 = interr upt on r ising edge of rb0/int pin 0 = interr upt on f alling edge of rb0/int pin bit 5: t0cs : tmr0 cloc k source se lect bit 1 = t r ansition on ra4/t0cki pin 0 = inter nal instr uction cycle cloc k (clk out) bit 4: t0se : tmr0 source edge sele ct bit 1 = increment on high-to-lo w tr ansition on ra4/t0cki pin 0 = increment on lo w-to-high tr ansition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate sel ect bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue tmr0 rate wdt rate
pic16c62x ds30235g -page 20 preliminary 1998 microchip technology inc. 4.2.2.3 intcon register the intcon register is a readab le and wr itab le register which contains the v ar ious enab le and ag bits f or all interr upt sources e xcept the compar ator module . see section 4.2.2.4 and section 4.2.2.5 f or a descr iption of the compar ator enab le and ag bits . note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). figure 4-10: intcon register (ad dress 0bh or 8bh) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -x gie p e ie t0ie inte rbie t0if intf rbif r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset -x = unkno wn at por reset bit7 bit0 bit 7: gie: global interr upt enab le bit 1 = enab les all un-mask ed interr upts 0 = disab les all interr upts bit 6: peie : p er ipher al i nterr upt enab le bit 1 = enab les all u n -mask ed per ipher al interr upts 0 = disab les all pe r ipher al interr upts bit 5: t0ie : tmr0 ov er o w interr upt en ab le bit 1 = enab les the tmr0 interr upt 0 = disab les the tmr0 interr upt bit 4: inte : rb0/int exter nal interr upt ena b le bit 1 = enab les the rb0/int e xter nal interr upt 0 = disab les the rb0/int e xter nal interr upt bit 3: rbie : rb p or t change interr upt e nab le bit 1 = enab les the rb por t change interr upt 0 = disab les the rb por t change interr upt bit 2: t0if : tmr0 ov er o w interr upt fla g bit 1 = tmr0 register has o v er o w ed (m ust be cleared in softw are) 0 = tmr0 register did not o v er o w bit 1: intf : rb0/int exter nal interr upt fla g bit 1 = the rb0/int e xter nal interr upt occurred (m ust be cleared in softw are) 0 = the rb0/int e xter nal interr upt did not occur bit 0: rbif : rb p or t change interr upt fla g bit 1 = when at least one of the rb7:rb4 pins changed state (m ust be cleared in softw are) 0 = none of the rb7:rb4 pins ha v e changed state
1998 microchip technology inc. preliminary ds30235g -page 21 pic16c62x 4.2.2.4 pie1 register this register contains the individual enab le bit f or the compar ator i nterr upt . figure 4-11: pie1 register (ad dress 8ch) 4.2.2.5 pir1 register this register contains the individual ag bit f or the compar ator interr upt. figure 4-12: pir1 register (ad dress 0ch) u- 0 r/w -0 u- 0 u- 0 u- 0 u- 0 u- 0 u- 0 cmie r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: cmie : compar ator interr upt enab le bit 1 = enab les the compar ator interr upt 0 = disab les the compar ator interr upt bit 5-0: unimplemented : read as '0' note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user softw are should ensure the appropr iate interr upt ag bits are clear pr ior to enab ling an interr upt. u- 0 r/w -0 u- 0 u- 0 u- 0 u- 0 u- 0 u- 0 cmif r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as'0' bit 6: cmif : compar ator interr upt flag bit 1 = compar ator input has changed 0 = compar ator input has not changed bit 5-0: unimplemented : read as '0'
pic16c62x ds30235g -page 22 preliminary 1998 microchip technology inc. 4.2.2.6 pcon register the pcon register contains ag bits to diff erentiate betw een a p o w er-on reset, an e xter nal mclr reset, wdt reset or a bro wn-out reset. note: bor is unkno wn on p o w er-on reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bor is cleared, indicating a bro wn-out has occurred. the bor status bit is a "don't care" and is not necessar ily predictab le if the bro wn-out circuit is disab led (b y prog r amming bo r en bit in the con gur ation w ord). figure 4-13: pcon register (ad dress 8e h ) u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 por bo r r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: re ad as '0' bit 1: por : p o w er-on reset status bit 1 = no p o w er-on reset occurred 0 = a p o w er-on reset occurred (m ust be set in softw are after a p o w er-on re set occurs) bit 0: bor : bro wn-out reset status bit 1 = no bro wn-out reset occurred 0 = a bro wn-out reset occurred (m ust be set in softw are after a bro wn-out reset occurs)
1998 microchip technology inc. preliminary ds30235g -page 23 pic16c62x 4.3 pcl and pcla th the prog r am counter (pc) is 13-bits wide . the lo w b yte comes from the pcl register , which is a readab le and wr itab le register . the high b yte (pc<12:8>) is not directly readab le or wr itab le and comes from pcla th. on an y reset, the pc is cleared. figure 4-14 sho ws the tw o situations f or the loading of the pc . the upper e xample in the gure sho ws ho w the pc is loaded on a wr ite to pcl (pcla th<4:0> ? pch). the lo w er e xample in the gure sho ws ho w the pc is loaded dur ing a call or goto instr uction (pcla th<4:3> ? pch). figure 4-14: loading of pc in diff erent situations 4.3.1 computed goto a computed go t o is accomplished b y adding an offset to the prog r am counter ( addwf pcl ). when doing a tab le read using a computed go t o method, care should be e x ercised if the tab le location crosses a pcl memor y boundar y (each 256 b yte b loc k). ref er to the application note ?mplementing a t ab le read" (an556). pc 12 8 7 0 5 pcla th<4:0> pcla th instr uction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pcla th<4:3> pch pcl 8 7 2 pcla th pch pcl pcl as destination 4.3.2 stac k the pic16c62x f a m ily has an 8 le v el deep x 13-bit wide hardw are stac k ( figure 4-2 and figure 4-3 ). the stac k space is not par t of either prog r am or data space and the stac k pointer is not readab le or wr itab le . the pc is pushed onto t he stac k when a call instr uction is e x ecuted or an interr upt causes a br anch. the stac k is pop ed in the e v ent of a return, retlw or a retfie instr uction e x ecution. pcla th is not aff ected b y a push or pop oper ation. the stac k oper ates as a circular b uff er . t his means that after the stac k has been pushed eight times , the ninth push o v erwr ites the v alue that w as stored from the rst push. t he tenth push o v erwr ites the second push (and so on). note 1: there are no st a tus bits to indicate stac k o v er o w or stac k under o w conditions . note 2: there are no instr uctions / mnemonics call e d push or pop . these are actions tha t occur from the e x ecution of the cal l , return, retlw and retfie inst r uctions , or the v ector ing to an inte r r upt address .
pic16c62x ds30235g -page 24 preliminary 1998 microchip technology inc. 4.4 indirect ad dressing, indf and fsr register s the indf register is not a ph ysical register . addressing the indf register will cause i ndirect addressing. indirect addressing is possib le b y using the indf reg- ister . an y instr uction using the indf register actually accesses data pointed to b y the le select register (fsr). reading indf itself indirectly will produce 00h. wr iting to the indf register indirectly results in a no-oper ation (although status bits ma y be aff ected). an eff ectiv e 9-bit address is obtained b y concatenating the 8-bit fsr register and the irp bit (st a tus<7>), as sho wn in figure 4-15 . ho w e v er , irp is not used in the pic16c62x . a simple prog r am to clear ram location 20h-2fh using indirect addressing is sho wn in example 4-1 . example 4-1: indirect ad dressing movlw 0x20 ;initialize pointe r mo vw f fsr ;to ram n ext clrf indf ;clear indf register incf fsr ;inc pointer b tfss fsr,4 ;all done? goto next ;no clear next ;yes continue continue: figure 4-15: direct/indirect ad dressing pic16c62x f or memor y map detail see ( figure 4-4 , figure 4-5 , figure 4-6 and figure 4-7 ) . note 1: the rp1 and irp bits are reser v ed, alw a ys maintain these bits clear . data memor y indirect ad dressing direct ad dressing bank select location select (1) rp1 rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180h 1ffh 00 h 7f h bank 0 bank 1 bank 2 bank 3 not used
1998 microchip technology inc. preliminary ds30235g -page 25 pic16c62x 5.0 i/o p or ts the pic16c62x ha v e tw o por ts , por t a and por tb . some p ins f or these i/o por ts are m ultiple x ed with an alter nate function f or the per ipher al f eatures on the de vice . in gener al, when a per ipher al is enab led, that pin ma y not be used as a gener al pur pose i/o pin. 5.1 por t a and trisa register s por t a is a 5-bit wide latch. ra4 is a schmitt t r igger input and an open dr ain output. p or t ra4 is m ultiple x ed with the t0cki cloc k input. all other ra por t pins ha v e schmitt t r igger input le v els and full cmos output dr iv ers . all pins ha v e data direction bits (tris registers) which can con g- ure these pins as input or output. a '1' in the trisa register puts the corresponding output dr iv er in a hi- impedance mode . a '0' in the trisa register puts the contents of the output latch on the selected pin(s). reading the por t a register reads the status of the pins whereas wr iting to it will wr ite to the por t latch. all wr ite oper ations are read-modify-wr ite oper ations . so a wr ite to a por t implies that the por t pins are rst read, then this v alue is modi ed and wr itten to the por t data latch. t he p or t a pins are m ultiple x ed with compar ator and v oltage ref erence functions . the oper ation of these pins are selected b y control bits in the cmcon ( compar ator control register) register and the vrcon (v oltage ref erence control register) register . when selected as a compar ator input, these pins will read as '0's . figure 5-1: bloc k dia gram of ra1:ra0 pins note: i/o pins ha v e protection diodes to v dd and v ss . data b us q d q ck p n wr p or t a wr tris a data latch tris latch rd tris a rd por t a analog v ss v dd i/o pin q d q ck input mode d q en t o compar ator schmitt t r igger input buff er trisa controls the direction of the ra pins , e v en when the y are being used as compar ator inputs . the user m ust mak e sure to k eep the pins con gured as inputs when using them as compar ator inputs . the ra2 pin will also function as the output f or the v oltage ref erence . when in this mode , the v ref pin is a v er y h igh impedance output. the user m ust con gure trisa<2> bit as an input and use h igh impedance loads . in one of the compar ator modes de ned b y the cmcon register , pins ra3 and ra4 become outputs of the compar ators . the trisa<4:3> bits m ust be cleared to enab le outputs to use this function. example 5-1: initializing por t a figure 5-2: bloc k dia gram of ra2 pin note: on reset, the trisa register is set to all inputs . the digital inputs are disab led and the compar ator inputs are f orced to g round to reduce e xcess current consumption. clrf porta ; initialize porta by setting ;output data latches movlw 0x07 ;turn comparators off and movwf cmcon ;enable pins for i/o ; functions bsf status, rp0 ;select bank1 movlw 0x 1f ;value used to initialize ;data direction movwf trisa ;set ra< 4: 0> as inputs ;trisa<7: 5> are always ;read as '0'. note: i/o pins ha v e protection diodes to v dd and v ss . data b us q d q ck p n wr p or t a wr tris a data latch tris latch rd trisa rd por t a analog v ss v dd ra2 pin q d q ck input mode d q en t o compar ator schmitt t r igger input buff er v roe v ref
pic16c62x ds30235g -page 26 preliminary 1998 microchip technology inc. figure 5-3: bloc k dia gram of ra3 pin figure 5-4: bloc k dia gram of ra4 pin data b us q d q ck p n wr p or t a wr tris a data latch tris latch rd tris a rd por t a analog v ss v dd ra3 pin q d q ck d q en t o compar ator schmitt t r igger input buff er input mode compar ator output compar ator mode = 110 note: i/o pins ha v e protection diodes to v dd and v ss data b us q d q ck n wr p or t a wr tris a data latch tris latch rd trisa rd por t a v ss ra4 pin q d q ck d q en tmr0 cloc k input schmitt t r igger input buff er compar ator output compar ator mode = 110 note: ra4 has protection d iodes to v ss only
1998 microchip technology inc. preliminary ds30235g -page 27 pic16c62x t ab le 5-1: por t a functions t ab le 5-2: summar y of register s associated wi th p or t a name bit # buff er t ype function ra0/an0 bit0 st input/output or compar ato r input ra1/an1 bit1 st input/output or compar ato r input ra2/an2/v ref bit2 st input/output or compar ator input or v ref output ra3/an3 bit3 st input/output or compar ator input/output ra4/t0cki bit4 st input/output or e xter nal cloc k input f or tmr0 or compar ator output . output is open dr ain type . legend: st = schmitt t r igger input ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 05h por t a ra4 ra3 ra2 ra1 ra0 ---x 0000 ---u 0000 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vr oe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: ?= unimplemented locations , read as ?? u = unchanged, x = unkno wn note: note: shaded bits are not used b y por t a.
pic16c62x ds30235g -page 28 preliminary 1998 microchip technology inc. 5.2 por tb and trisb register s por tb is an 8-bit wide bi-directional por t. the corresponding data direction register is trisb . a '1' in the trisb register puts the corresponding output dr iv er in a high impedance mode . a '0' in the trisb register puts the contents of the output latch on the selected pin(s). r eading por tb register reads the status of the pins , whereas wr iting to it will wr ite to the por t latch. all wr ite oper ations are read-modify-wr ite oper ations . so a wr ite to a por t implies that the por t pins are rst read, then this v alue is modi ed and wr itten to the por t data latch. each of the por tb pins has a w eak inter nal pull-up ( ? 200 m a typical). a single control bit can tur n on all the pull-ups . this is done b y clear ing the rbpu (option<7>) bit. the w eak pull-up is automatically tur ned off when the por t pin is con gured as an output. the pull-ups are disab led on p o w er-on reset. f our of por tb s pins , rb7:rb4, ha v e an interr upt on change f eature . only pins con gured as inputs can cause this interr upt to occur (i.e ., an y rb7:rb4 pin con gured as an output is e xcluded from the interr upt on change compar ison). the input pins (of rb7:rb4) are compared with the old v alue latched on the last read of por tb . the ?ismatch outputs of rb7:rb4 are or?d together to gener ate the rbif interr upt ( ag latched in intcon<0>). figure 5-5: bloc k dia gram of r b 7:rb4 p i ns data latch f rom other rbpu (2) p v dd i/o q d ck q d ck q d en q d en data b us wr p or t b wr tris b set rbif tris latch rd tris b rd p or t b rb 7 : rb 4 p ins w eak pull-up rd p or t latch ttl input buff er pin (1) note 1: i /o pins ha v e diode protection to v dd and v ss . note 2: t risb = 1 enab les w eak pull-up if rbpu = '0' (option<7>). st buff er rb7:rb6 in ser ial prog r amming mode q q this interr upt can w ak e the de vice from sleep . the user , in the interr upt ser vice routine , can clear the interr upt in the f ollo wing manner : a) an y rea d or wr ite of por tb . this will end the mismatch condition. b) clear ag bit rbif . a mismatch condition will contin ue to set ag bit rbif . reading por tb will end the mismatch condition, and allo w ag bit r bif t o be cleared. this interr upt on mismatch f eature , together with softw are con gur ab le pull-ups on these f our pins allo w easy interf ace to a k e y pad and mak e it possib le f or w ak e-up on k e y-depression. (see an552 in the microchip e mbedded control handbook .) the inte rr upt on change f eature is recommended f or w ak e-up on k e y depression oper ation and oper ations where por tb is only used f or th e interr upt on change f eature . p olling of por tb is not recommended while using the interr upt on change f eature . figure 5-6: blo c k dia gram of rb3:rb0 pi n s note: if a change on the i/o pin should occur when the read oper ation is being e x ecuted (star t of the q2 cycle), then the rbif inter- r upt ag ma y not get set. data latch rbpu (2) p v dd q d ck d ck q d en data b us wr p or t b wr tris b rd tris b rd p or t b w eak pull-up rd p or t rb0/int i/o pin (1) ttl input buff er note 1: i /o pins ha v e diode protection to v dd and v ss . note 2: t risb = 1 enab les w eak pull-up if rbpu = ' 0 ' (option<7>). st buff er q q q
1998 microchip technology inc. preliminary ds30235g -page 29 pic16c62x t ab le 5-3: por tb functions t ab le 5-4: summar y of register s associated wi th p or tb name bit # buff er t ype function rb0/int bit0 ttl/st (1) input/output or e xter nal interr upt input. inter nal softw are prog r ammab le w eak pull-up . rb1 bit1 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb2 bit2 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb3 bit3 ttl input/output pin. inter nal softw are prog r ammab le w eak pull-up . rb4 bit4 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb5 bit5 ttl input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . rb6 bit6 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming cloc k pin. rb7 bit7 ttl/st (2) input/output pin (with interr upt on change). inter nal softw are prog r ammab le w eak pull-up . ser ial prog r amming data pin. legend: st = schmitt t r igger , ttl = ttl input note 1: this b uff er is a schmitt t r igger input when con gured as the e xter nal interr upt. note 2: this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 06h por tb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 note: s haded b i ts are not used b y por tb . u = unchanged x = unkno wn
pic16c62x ds30235g -page 30 preliminary 1998 microchip technology inc. 5.3 i/o pr ogramming considerations 5.3.1 bi-directional i/o p or ts an y instr ucti on which wr ites , oper ates i nter nally as a read f ollo w ed b y a wr ite oper ation. the bcf and bsf instr uctions , f or e xample , read the register into the cpu , e x ecute the bit oper ation and wr ite the result bac k to the register . caution m ust be used when these instr uctions are applied to a por t with both inputs and outputs de ned. f or e xample , a bsf oper ation on bit5 of por tb will cause all eight bits of por tb to be read into the cpu . then the bsf oper ation tak es place on bit5 and por tb is wr itten to the output latches . if another bit of por tb is used as a bidirectional i/o pin ( e .g., b it0) and it is de ned as an input at this time , the input signal present on the pin itself w ould be read into the cpu and re-wr itten to the data latch of this par ticular pin, o v erwr iting the pre vious content. as long as the pin sta ys in the input mode , no prob lem occurs . ho w e v er , if bit0 is s witched into output mode later on, the content of the data latch ma y no w be unkno wn. reading the por t register , reads the v alues of the por t pins . wr iting to the por t register wr ites the v alue to the por t latch. when using read modify wr ite instr uctions (e x. bcf, bsf , etc.) on a por t , the v alue of the por t pins is read, the desired oper ation is done to this v alue , and this v alue is then wr itten to the por t latch. example 5-2 sho ws the eff ect of tw o sequential read-modify-wr ite instr uctions (e x., bcf, bsf , etc.) on an i/o por t . a pin activ ely outputting a lo w or high should not be dr iv en from e xter nal de vices at the same time in order to change the le v el on this pin (?ired-or? ?ired-and?. the resulting high output currents ma y damage the chip . example 5-2: read-modify-write instructions on an i/o p or t 5.3.2 successiv e oper ations on i/o p or ts the actual wr ite to an i/o por t happens at the end of an instr uction cycle , whereas f or reading, the data m ust be v alid at the beginning of the instr uction cycle ( figure 5-7 ). theref ore , care m ust be e x ercised if a wr ite f ollo w ed b y a read oper ation is carr ied out on the same i/o por t. the sequence of instr uctions should be such to allo w the pin v oltage to stabiliz e (load dependent) bef ore the ne xt instr uction which causes that le to be read into the cpu is e x ecuted. otherwise , the pre vious state of that pin ma y be read into the cpu r ather than the ne w state . when in doubt, it is better to separ ate these instr uctions with a nop or another instr uction not accessing this i/o por t. ; ; initial port set tings: portb<7:4> inputs ; portb<3:0> outputs ; ; portb<7:6> have external pull-up and are not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status, r p0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ; note that the user may have expected the pin ; values to be 00pp pppp. the 2nd bcf caused ; rb7 to be latched as the pin value (high). figure 5-7: successive i/o operation note: this example shows write to portb followed by a read from portb. note that: data setup time = (0.25 t cy - t pd ) where t cy = instruction cycle and t pd = propagation delay of q1 cycle to output valid. therefore, at higher clock frequencies, a write followed by a read may be problematic. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 rb <7:0> port pin sampled here pc pc + 1 pc + 2 pc + 3 nop nop movf portb, w read portb movwf portb write to portb pc instruction fetched t pd execute movwf portb execute movf portb, w execute nop rb7:rb0
1998 microchip technology inc. preliminary ds30235g -page 31 pic16c62x 6.0 timer0 module the timer0 module timer/counter has the f ollo wing f eatures: 8-bit timer/counter readab le and wr itab le 8-bit softw are prog r ammab le prescaler inter nal or e xter nal cloc k select interr upt on o v er o w from ffh to 00h edge select f or e xter nal cloc k figure 6-1 is a simpli ed b loc k diag r am of the timer0 module . timer mode is selected b y clear ing the t0cs bit (option<5>). in timer mode , the tmr0 will increment e v er y instr uction cycle (without prescaler). if timer0 is wr itten, the increment is inhibited f or the f ollo wing tw o cycles ( figure 6-2 and figure 6-3 ). the user can w or k around this b y wr iting an adjusted v alue to t mr0 . counter mode is selected b y setting the t0cs bit. in this mode timer0 will increment either on e v er y r ising or f alling edge of pin ra4/t0cki. the incrementing edge is deter mined b y the source edge (t0se) control bit (option<4>). clear ing the t0se bit selects the r ising edge . restr ictions on the e xter nal cloc k input are d iscussed in detail in section 6.2 . the prescaler is shared betw een the timer0 module and the w atchdog timer . the prescaler assignment is controlled in softw are b y the control bit psa (option<3>). clear ing the psa bit will assign the prescaler to timer0 . the prescaler is not readab le or wr itab le . when the prescaler is assigned to the timer0 module , prescale v alue of 1:2, 1:4, ..., 1:256 are selectab le . section 6.3 details the oper ation of the prescaler . 6.1 timer0 interrupt timer0 interr upt is gener ated when the tmr0 regi s ter timer/counter o v er o ws from ffh to 00h. this o v er o w sets the t0if bit. the interr upt can be mask ed b y clear ing the t0ie bit (intcon<5>). the t0if bit (intcon<2>) m ust be cleared in softw are b y the timer0 module interr upt ser vice routine bef ore re-enab ling this interr upt. the tim e r0 interr upt cannot w ak e the processor from sleep since the timer is shut off dur ing sleep . see figure 6-4 f or timer0 interr upt timing. figure 6-1: timer0 bl o c k dia gram figure 6-2: timer0 (tmr0) timing: internal cloc k/no prescaler note 1: bits t0se, t0cs , ps2, ps1, ps0 and psa are located in the option register . 2: the prescaler is shared with w atchdog timer ( figure 6-6 ) ra 4 /t0cki t0se 0 1 1 0 pin t0cs f osc /4 prog r ammab le prescaler sync with inter nal cloc ks tmr0 psout (2 t cy dela y) psout data b us 8 set flag bit t0if on ov er o w psa ps2:ps0 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0+1 nt0+2 t0 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instr uction ex ecuted
pic16c62x ds30235g -page 32 preliminary 1998 microchip technology inc. figure 6-3: timer0 timing: internal cloc k/prescale 1:2 figure 6-4: timer0 interrupt tim i ng pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0 + 1 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instr uction ex ecute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clk out(3) tmr0 timer t0if bit (intcon<2>) feh gie bit (intcon<7>) instr uction flo w pc instr uction f etched pc pc +1 pc +1 0004h 0005h instr uction e x ecuted inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dumm y cycle dumm y cycle ffh 00h 01h 02h note 1: t0if interr upt ag is sampled here (e v er y q1). 2: interr upt latency = 3 t cy , where t cy = instr uction cycle time . 3: clk out is a v ailab le only in rc oscillator mode . interr upt latency time
1998 microchip technology inc. preliminary ds30235g -page 33 pic16c62x 6.2 using timer0 with external cloc k when an e xter nal cloc k input is used f or timer0 , it m ust meet cer tain requirements . the e xter nal cloc k requirement is due to inter nal phase cloc k (t osc ) synchronization. also , there is a dela y in the actual incrementing of timer0 after synchronization. 6.2.1 exter nal cloc k synchronization when no prescaler is used, the e xter nal cloc k input is the same as the prescaler output. the synchronization of t0cki with the inter nal phase cloc ks is accomplished b y sampling the prescaler output on the q2 and q4 cycles of the inter nal phase cloc ks ( figure 6-5 ). theref ore , it is necessar y f or t0cki to be high f or at least 2t osc (and a small rc dela y of 20 ns) and lo w f or at least 2t osc (and a small rc dela y of 20 ns). ref er to the electr ical speci cation of the desired de vice . when a prescaler is used, the e xter nal cloc k input is divided b y the asynchronous r ipple-counter type prescaler so that the prescaler output is symmetr ical. f or the e xter nal cloc k to meet the sampling requirement, the r ipple-counter m ust be tak en into account. theref ore , it is necessar y f or t0cki to ha v e a per iod of at least 4t osc (and a small rc dela y of 40 ns) divided b y the prescaler v alue . the only requirement on t0cki high and lo w time is that the y do not violate the minim um pulse width requirement of 10 ns . ref er to par ameters 40, 41 and 42 in the electr ical speci cation of the desired de vice . 6.2.2 timer0 increment dela y since the prescaler output is synchroniz ed with the inter nal cloc ks , there is a small dela y from the time the e xter nal cloc k edge occurs to the time the tmr0 is actually incremented. figure 6-5 sho ws the dela y from the e xter nal cloc k edge to the timer incrementing. figure 6-5: timer0 timing with external cloc k q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 exter nal cloc k input or prescaler output (2) exter nal cloc k/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: dela y from cloc k input change to timer0 increment is 3 t osc to 7 t osc. (dur ation of q = t osc). theref ore , the error in measur ing the inter v al betw een t w o edges on timer0 input = 4 t osc max. 2: exter nal cloc k if no prescaler selected, prescaler output otherwise . 3: the arro ws indicate the points in time where sampling occurs . (3) (1)
pic16c62x ds30235g -page 34 preliminary 1998 microchip technology inc. 6.3 prescaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a postscaler f or the w atchdog timer , respectiv ely ( figure 6-6 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that there is only one prescaler a v ailab le which is m utually e xclusiv e betw een the timer0 module and the w atchdog timer . thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the w atchdog timer , and vice-v ersa. the psa and ps2 : ps0 bits (option<3:0>) deter mine the prescaler assignment and prescale r atio . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 reg i ster (e .g. , clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the w atchdog timer . the prescaler is not readab le or wr itab le . figure 6-6: bloc k dia gram o f the timer0 /wdt prescaler t0cki t0se pin m u x clk out (=f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1mux m u x m u x w atchdog timer psa 0 1 0 1 wdt time-out ps0 - ps2 8 note: t0se, t0cs , psa, ps0-ps2 are bits in the option register . psa wdt enab le bit m u x 0 1 0 1 data bus set ag bit t0if on ov er o w 8 psa t0cs
1998 microchip technology inc. preliminary ds30235g -page 35 pic16c62x 6.3.1 switching prescaler assignment the prescaler assignment is fully under softw are control ( i.e ., it can be changed ?n the y dur ing prog r am e x ecution ) . t o a v oid an unintended de vice reset , the f ollo wing instr uction sequence ( example 6-1 ) m ust be e x ecuted when changing the prescaler assignment from timer0 to wdt . example 6-1: c hanging prescaler ( timer0 ? wdt) 1. bcf status, rp0 ;skip if already in ; bank 0 2. clrwdt ;clear wdt 3. clrf tmr0 ;clear tmr0 & prescaler 4. bsf status, rp0 ;bank 1 5. movlw '00101111? ; ;these 3 lines (5, 6, 7) 6. movwf option ; are required only if ; desired ps<2:0> are 7. clrwdt ; 000 or 001 8. movlw '00101xxx? ;set postscaler to 9. movwf option ; desired wdt rate 10. bcf status, rp0 ;return to bank 0 t o change prescaler from the wdt to the tmr0 module use the sequence sho wn in example 6-2 . this precaution m ust be tak en e v en if the wdt is disab led. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler bsf status, rp0 movlw b 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source movwf option _reg bcf status, rp0 t able 6-1: register s associated with timer0 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 01h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: ?= unimplemented locations , read as ? . note: s haded b i ts are not used b y tmr0 module . u = unchanged x = unkno wn
pic16c62x ds30235g -page 36 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds30235g -page 37 pic16c62x 7.0 comparator module the compar ator module contains tw o analog compar ators . the inputs to the compar ators are m ultiple x ed with the ra0 through ra3 pins . the on-chip v oltage ref erence ( section 8.0 ) can also be an input to the compar ators . the cmcon register , sho wn in figure 7-1 , controls the compar ator input and output m ultiple x ers . a b loc k diag r am of the compar ator is sho wn in figure 7-2 . figure 7-1: cmcon register (ad dress 1f h ) r-0 r-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 c2out c1out cis cm2 cm1 cm0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: c2out : compar ator 2 output 1 = c2 v in + > c2 v in 0 = c2 v in + < c2 v in bit 6: c1out : compar ator 1 output 1 = c1 v in + > c1 v in 0 = c1 v in + < c1 v in bit 5-4: unimplemented : read as '0' bit 3: cis : compar ator input switch when c m <2:0>: = 001: 1 = c1 v in ?connects to ra3 0 = c1 v in ?connects to ra0 when cm < 2:0> = 010: 1 = c1 v in ?connects to ra3 c2 v in ?connects to ra2 0 = c1 v in ?connects to ra0 c2 v in ?connects to ra1 bit 2-0: cm < 2:0> : compar ator mode figure 7-2 .
pic16c62x ds30235g -page 38 preliminary 1998 microchip technology inc. 7.1 comparator con guration there are eight modes of oper ation f or the compar ators . the cmcon register is used to select the mode . figure 7-2 sho ws the eight possib le modes . the trisa register controls the data direction of the com- par ator pins f or each mode . if the compar ator mode is changed, the compar ator output le v el ma y not be v alid f or the speci ed mode change dela y sho wn in t ab le 12-2 . note: compar ator interr upts should be disab led dur ing a compar ator mode change other- wise a f alse interr upt ma y occur . figure 7-2: comparator i/o operating modes - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 a a cm < 2:0> = 000 - + c2 v in - v in + off (read as '0') ra1/an1 ra2/an2 a a - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 d d cm<2:0 > = 111 - + c2 v in - v in + off (read as '0') ra1/an1 ra2/an2 d d - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm< 2 :0> = 100 - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a f rom v ref module - + c1 v in - v in + c1out ra0/an0 ra3/an3 a d - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm < 2:0> = 011 ra4 open dr ain - + c1 v in - v in + c1out ra0/an0 ra3/an3 a d - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 110 - + c1 v in - v in + off (read as '0') ra0/an0 ra3/an3 d d cm<2 : 0> = 101 - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a - + c1 v in - v in + c1out ra0/an0 ra3/an3 a a - + c2 v in - v in + c2out ra1/an1 ra2/an2 a a cm<2:0> = 0 01 cis=0 cis=1 compar ators reset t w o independent compar ators t w o common ref erence compar ators one independent compar ator three inputs multiple x ed to t w o common ref erence compar ators with outputs f our inputs multiple x ed to compar ators off t w o compar ators t w o compar ators cm<2: 0 > = 010 cis=0 cis=1 cis=0 cis=1 a = analog input, p or t reads zeros alw a ys d = digital input cis = cm c on<3>, compar ator input switch
1998 microchip technology inc. preliminary ds30235g -page 39 pic16c62x the code e xample in example 7-1 depicts the steps required to con gure the compar ator module . ra3 and ra4 are con gured as digital output. ra0 and ra1 are con gured as the v - inputs and ra2 as the v+ input to both compar ators . example 7-1: in itializing comparator module 7.2 comparator operation a single compar ator is sho wn in figure 7-3 along with the relationship betw een the analog input le v els and the digital output. when the analog input at v in + is less than the analog input v in ? the output of the compar ator is a digital lo w le v el. when the analog input at v in + is g reater than the analog input v in ? the output of the compar ator is a digital high le v el. the shaded areas of the output of the compar ator in figure 7-3 r epresent the uncer tainty due to input offsets and response time . flag_reg equ 0x20 clrf flag_reg ;init flag register clrf porta ;init porta movf cmcon, w ;load comparator bits andlw 0xc0 ;mask comparator bits iorwf flag_reg,f ;store bits in flag register movlw 0x03 ;init comparator mode movwf cmcon ;cm<2:0> = 011 bsf status,rp0 ;select bank1 movlw 0x07 ;initialize data direction movwf trisa ;set ra<2:0> as inputs ;ra<4:3> as outputs ;trisa<7:5> always read ? bcf status,rp0 ;select bank 0 call delay 10 ;10 m s delay movf cmcon,f ;rea d cmco n t o en d chang e condition bcf pir1,cmif ;clear pending interrupts bsf status,rp0 ;select bank 1 bsf pie1,cmie ;enable comparator interrupts bcf status,rp0 ; select bank 0 bsf intcon,peie ;enable peripheral interrupts bsf intcon,gie ;global interrupt enable 7.3 comparator ref erence an e xter nal or inter nal ref erence signal ma y be used depending on the compar ator oper ating mode . the analog signal that is present at v in ?is compared to the signal at v in +, and the digital output of the compar ator is adjusted accordingly ( figure 7-3 ). figure 7-3: single co mparator 7.3.1 external reference signal when e xter nal v oltage ref erences are used, the compar ator module can be con gured to ha v e the com- par ators oper ate from the same or diff erent ref erence sources . ho w e v er , threshold detector applications ma y require the same ref erence . the ref erence signal m ust be betw een v ss and v dd , and can be applied to either pin of the compar ator(s). 7.3.2 internal reference signal the compar ator module also allo ws the selection of an inter nally gener ated v oltage ref erence f or the compar ators . section 13, instr uction sets , contains a detailed descr iption of the v oltage ref erence module that pro vides this signal. the inter nal ref erence signal is used when the compar ators are i n mode cm<2: 0 > =010 ( figure 7-2 ). in this mode , the inter nal v oltage ref erence is applied to the v in + pin of both com- par ators . + v in + v in output v in v in+ output
pic16c62x ds30235g -page 40 preliminary 1998 microchip technology inc. 7.4 comparator response time response time is the minim um time , after selecting a ne w ref erence v oltage or input source , bef ore the compar ator output is guar anteed to ha v e a v alid le v el. if the inter nal ref erence is changed, the maxim um dela y of the inter nal v oltage ref erence m ust be considered when using the compar ator outputs . otherwise the maxim um dela y of the compar ators should be used ( t ab le 12-2 ) . 7.5 comparator outputs the compar ator outputs are read through the cmcon register . these bits are read only . the compar ator outputs ma y also be directly output to the ra3 and ra4 i/o pins . when the cm < 2:0 > = 110, m ultiple xors in the output path of the ra3 and ra4 pins will s witch and the output of each pin will be the unsynchroniz ed output of the compar ator . the uncer tainty of each of the compar ators is related to the input offset v oltage and the response time giv en in the speci cations . figure 7-4 sho ws the compar ator output b loc k diag r am. the trisa bits will still function as an output enab le/disab le f or the ra3 and ra4 pins while in this mode . note 1: when reading the por t register , all pins con gured as analog inputs will read as a ?? pins con gured as digital inputs will con v er t an analog input according to the schmitt t r igger input speci cation. 2: analog le v els on an y pin that is de ned as a digital input ma y cause the input b uff er to consume more current than is speci ed. figure 7-4: co mparator o u tput bloc k dia gram d q en t o ra3 or ra4 pin bus data rd cmcon set mul tiplex cmif bit - + d q en cl p or t pins rd cmcon nreset f rom other compar ator
1998 microchip technology inc. preliminary ds30235g -page 41 pic16c62x 7.6 comparator interrupts the compar ator interr upt ag is set whene v er there is a change in the output v alue of either compar ator . softw are will need to maintain inf or mation about the status of the output bits , as read from cmcon<7:6>, to deter mine the actual change that has occurred. the cmif bit, pir1<6>, is the compar ator interr upt ag. the cmif bit m ust be reset b y clear ing ?? since it is also possib le to wr ite a '1' to this register , a sim ulated interr upt ma y be initiated. the cmie bit (pie1<6>) and the peie bit (intcon<6>) m ust be set to enab le the interr upt. in addition, the gie bit m ust also be set. if an y of these bits are clear , the interr upt is not enab led, though the cmif bit will still be set if an interr upt condition occurs . the user , in the interr upt ser vice routine , can clear the interr upt in the f ollo wing manner : a) an y read or wr ite of cmcon. this will end the mismatch condition. b) clear ag bit cmif . a mismatch condition will contin ue to set ag bit cmif . reading cmcon will end the mismatch condition, and allo w ag bit cmif to be cleared. 7.7 c omparator operation during sleep when a compar ator is activ e and the de vice is placed in sleep mode , the compar ator remains activ e and the interr upt is functional if enab led. this interr upt will note: if a change in the cmcon register (c1out or c2out) should occur when a read oper ation is being e x ecuted (star t of the q2 cycle), then the cmif (pir1<6>) interr upt ag ma y not get set. w ak e up the de vice from sleep mode when enab led. while the compar ator is po w ered-up , higher sleep currents than sho wn in the po w er do wn current speci cation will occur . each compar ator that is oper ational will consume additional current as sho wn in the compar ator speci cations . t o minimiz e po w er consumption while in sleep mode , tur n off the compar ators , cm < 2 :0 > = 111, bef ore enter ing sleep . if the de vice w ak es-up from sleep , the contents of the cmcon register are not aff ected. 7.8 eff ects of a reset a de vice reset f orces the cmcon register to its reset state . this f orces the compar ator module to be in the compar ator reset mode , cm2: cm 0 = 000. this ensures that all potential inputs are analog inputs . de vice current is minimiz ed when analog inputs are present at reset time . the compar ators will be po w ered-do wn dur ing the reset inter v al. 7.9 analog input connection considerations a simpli ed circuit f or an analog input is sho wn in figure 7-5 . since the analog pins are connected to a digital output, the y ha v e re v erse biased diodes to v dd and v ss . the analog input theref ore , m ust be betw een v ss and v dd . if the input v oltage de viates from this r ange b y more than 0.6v in either direction, one of the diodes is f orw ard biased and a latch-up ma y occur . a maxim um source impedance of 10 k w is recommended f or the analog sources . an y e xter nal component connected to an analog input pin, such as a capacitor or a zener diode , should ha v e v er y little leakage current. figure 7-5: ana log input model v a r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r i c i leakage 500 na v ss legend c pin = input capacitance v t = threshold v oltage i leakage = leakage current at the pin due t o v ar ious j unctions r ic = interconnect resistance r s = source impedance v a = analog v oltage
pic16c62x ds30235g -page 42 preliminary 1998 microchip technology inc. t able 7-1: register s associated with comparator module legend: x = u nkno wn u = unchanged - = u nimplemented, read as "0" ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vr oe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 cmif -0-- ---- -0-- ---- 8ch pie1 cmie -0-- ---- -0-- ---- 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111
1998 microchip technology inc. preliminary ds30235g -page 43 pic16c62x 8.0 v olta g e ref erence module the v oltage ref erence is a 16-tap resistor ladder netw or k that pro vides a selectab le v oltage ref erence . the resistor ladder is segmented to pro vide tw o r anges of v ref v alues and has a po w er-do wn function to conser v e po w er when the ref erence is not being used. the vrcon register controls the oper ation of the ref erence as sho wn in figure 8-1 . the b loc k diag r am is giv en in figure 8-2 . 8.1 con guring the v olta g e ref erence the v oltage ref erence can output 16 distinct v oltage le v els f or each r ange . the equations used to calculate the output of the v oltage ref erence are as f ollo ws: if v rr = 1: v ref = (v r <3:0>/24) x v dd if v rr = 0: v ref = (v dd x 1/4) + (v r <3:0>/32) x v dd the setting time of the v oltage ref erence m ust be considered when changing the v ref output ( t ab le 12-2 ). example 8-1 sho ws an e xample of ho w to con gure the v oltage ref erence f or an output v oltage of 1.25v with v dd = 5.0v . figure 8-1: vrcon register(ad dress 9f h ) figure 8-2: v olta g e ref erence bloc k dia gram r/w -0 r/w -0 r/w -0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 v ren v r oe v rr v r3 v r2 v r1 v r0 r = readab le bit w = wr itab le bit u = unimplemented bit, read as ? - n = v alue at por reset bit7 bit0 bit 7: v ren : v ref enab le 1 = v ref circuit po w ered on 0 = v ref circuit po w ered do wn, no i dd dr ain bit 6: v r oe : v ref output enab le 1 = v ref is output on ra2 pin 0 = v ref is disconnected from ra2 pin bit 5: v rr : v ref range selection 1 = lo w range 0 = high range bit 4: unimplemented : read as '0' bit 3-0: v r < 3 :0> : v ref v alue selection 0 v r [3:0] 15 when v rr = 1: v ref = (v r <3:0>/ 24) * v dd when v rr = 0: v ref = 1/4 * v dd + (v r <3:0>/ 32 ) * v dd note: r is de ned in t ab le 12-3 . v rr 8r v r 3 v r 0 (f rom vrcon<3:0>) 16-1 analog mux 8r r r r r v ren v ref 16 stages
pic16c62x ds30235g -page 44 preliminary 1998 microchip technology inc. example 8-1: v olta g e ref erence configuration 8.2 v olta g e ref erence accurac y/err or the full r ange of v ss to v dd cannot be realiz ed due to the constr uction of the module . the tr ansistors on the top and bottom of the resistor ladder netw or k ( figure 8-2 ) k eep v ref from approaching v ss or v dd . the v oltage ref erence is v dd der iv ed and theref ore , the v ref output changes with uctuations in v dd . the tested absolute accur acy of the v oltage ref erence can be f ound in t ab le 12-3 . 8.3 operation during sleep when the de vice w ak es up from sleep through an interr upt or a w atchdog timer time-out, the contents of the vrcon register are not aff ected. t o minimiz e current consumption in sleep mode , the v oltage ref erence should be disab led. movlw 0x02 ; 4 inputs muxed movwf cmcon ; to 2 comps. bsf status,rp0 ; go to bank 1 movlw 0x07 ; ra3-ra0 are movwf trisa ; outputs movlw 0xa6 ; enable v ref movwf vrcon ; low range ; set v r <3:0>=6 bcf status,rp0 ; go to bank 0 call delay10 ; 10 m s delay 8.4 eff ects of a reset a de vice reset disab les the v oltage ref erence b y clear- ing bit v ren (vrcon<7>). this reset also disconnects the ref erence from the ra2 pin b y clear ing bit v roe (vrcon<6>) and selects the high v oltage r ange b y clear ing bit v rr (vrcon<5>). the v ref v alue select bits , vrcon<3:0>, are also cleared. 8.5 connection considerations the v oltage ref erence module oper ates independently of the compar ator module . the output of the ref erence gener ator ma y be connected to the ra2 pin if the trisa<2> bit is set and the v roe bit, vrcon<6>, is set. enab ling the v oltage ref erence output onto the ra2 pin with an input signal present will increase cur- rent consumption. connecting ra2 as a digital output with v ref enab led will also increase current consump- tion. the ra2 pin can be used as a simple d/a output with limited dr iv e capability . due to the limited dr iv e capability , a b uff er m ust be used in conjunction with the v oltage ref erence output f or e xter nal connections to v ref . figure 8-3 sho ws an e xample b uff er ing technique . figure 8-3: v olta g e ref erence output buff er example t able 8-1: register s associated with v olta g e ref erence note: - = unimplemented, read as "0" ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 9fh vrcon vren vr oe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 v ref output + v ref module v oltage ref erence output impedance r (1) ra2 note 1: r is dependent upon the v oltage ref erence con gur ation vrcon<3:0> and vrcon<5>.
1998 microchip technology inc. preliminary ds30235g -page 45 pic16c62x 9.0 special features of the cpu special circuits to deal with the needs of real time appli- cations are w hat sets a microcontroller apar t from other processors . the pic16c62x f amily has a host of such f eatures intended to maximiz e system reliability , mini- miz e cost through elimination of e xter nal components , pro vide po w er sa ving oper ating modes and off er code protection. these are: 1. osc selection 2. reset p o w er-on reset (por) p o w er-up timer (pwr t) oscillator star t-up timer (ost) bro wn-out reset (bor) 3. interr upts 4. w atchdog timer (wdt) 5. sleep 6. code protection 7. id locations 8. in-circuit ser ial prog r amming the pic16c62x has a w atchdog timer which is controlled b y con gur ation bits . it r uns off its o wn rc oscillator f or added reliability . there are tw o timers that off er necessar y dela ys on po w er-up . one is the oscillator star t-up timer (ost), intended to k eep the chip in reset until the cr ystal oscillator is stab le . the other is the p o w er-up timer (pwr t), which pro vides a x ed dela y of 72 ms (nominal) on po w er-up only , designed to k eep the par t in reset while the po w er supply stabiliz es . there is also circuitr y to reset the de vice if a bro wn-out occurs which pro vides at least a 72 ms reset. with these three functions on-chip , most applications need no e xter nal reset circuitr y . the sleep mode is designed to off er a v er y lo w current po w er-do wn mode . the user can w ak e - up from sleep through e xter nal reset, w atchdog t imer w ak e-up or through an interr upt. se v er al oscillator options are also made a v ailab le to allo w the par t to t the application. the rc oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur ation bits are used to select v ar ious options .
pic16c62x ds30235g -page 46 preliminary 1998 microchip technology inc. 9.1 con guration bits the con gur ation bits can be prog r ammed (read as '0') or left unprog r ammed (read as '1') to select v ar ious de vice con gur ations . these bits are mapped in prog r am memor y location 2007h. the user will note that address 2007h is be y ond the user prog r am memor y space . in f act, it belongs to the special test/con gur ation memor y space (2000h ? 3fffh), which can be accessed only dur ing prog r amming. figure 9-1: configuration w or d cp1 cp0 (2) cp1 cp0 (2) cp1 cp0 (2) boren (1) cp1 cp0 (2) pwr te (1) wdte f0sc1 f0sc0 config address register: 2007h bit13 bit0 bit 13-8, cp<1:0>: code protection bit pairs (2) 5-4: code pr otection f or 2k pr ogram memor y 11 = prog r am memor y code protection off 10 = 0400h-07ffh code protected 01 = 0200h-07ffh code protected 00 = 0000h-07ffh code protected code pr otection f or 1k pr ogram memor y 11 = prog r am memor y code protection off 10 =prog r am memor y code protection on 01 = 0200h-03ffh code protected 00 = 0000h-03ffh code protected code pr otection f or 0.5k pr ogram memor y 11 = prog r am memor y code protection off 10 = prog r am memor y code protection of f 01 = prog r am memor y code protection of f 00 = 0000h-01ffh code protected bit 7 : unimplemented : read as '1' bit 6: boren : bro wn-out reset enab le bit (1) 1 = bor enab led 0 = bor disab led bit 3: pwr te : p o w er-up timer enab le bit (1, 3) 1 = pwr t disab led 0 = pwr t enab led bit 2: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enab ling bro wn-out reset automatically enab les p o w er-up timer (pwr t) regardless of the v alue of bit pwr te . w e recommend that whene v er bro wn-out reset is enab led, the p o w er-up timer is also enab led. 2: all of the cp1:cp0 pairs ha v e to be giv en the same v alue to enab le the code protection scheme listed. 3: unprog r ammed par ts def ault the p o w er-up timer disab led.
1998 microchip technology inc. preliminary ds30235g -page 47 pic16c62x 9.2 oscillator con gurations 9.2.1 oscillator t ypes the pic16c62x can be oper ated in f our diff erent oscillator options . the user can prog r am tw o con gur ation bits (fosc1 and fosc0) to select one of these f our modes: lp lo w p o w er cr ystal xt cr ystal/resonator hs high speed cr ystal/resonator rc resistor/capacitor 9.2.2 cr ystal oscillator / ceramic resonators in xt , lp or hs modes a cr ystal or cer amic resonator is connected to the osc1 and osc2 pins to estab lish oscillation ( figure 9-2 ). the pic16c62x oscillator design requires the use of a par allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers speci cations . when in xt , lp or hs modes , the de vice can ha v e an e xter nal cloc k source to dr iv e the osc1 pin ( figure 9-3 ). figure 9-2: cr ys tal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 9-3: exte rnal cloc k input operation (hs, xt or lp osc configuration) see t ab le 9-1 and t ab le 9-2 f or recommended v alues of c1 and c2. note: a ser ies resistor ma y be required f or a t str ip cut cr ystals . c1 c2 xt al osc2 rs osc1 rf sleep t o inter nal logic pic16c62x see note c loc k f rom e xt. system pic16c62x osc1 osc2 o pen t able 9-1: capacitor selection f or ceramic resonator s t able 9-2: capacitor selection f or cr ystal oscillator rang es characteriz ed: mode freq osc1 (c1) osc 2 (c2) xt 455 kh z 2.0 mhz 4.0 mhz 22 - 100 pf 15 - 68 pf 15 - 68 pf 22 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf h igher capacitance increases the stability of the oscillator b ut also increases the star t-up time . these v alues are f or design guidance only . since each resonator has its o wn char acter istics , the user should consult the resonator man- uf acturer f or appropr iate v alues of e xter nal components . mode freq osc1 (c1) osc2 (c2) lp 32 khz 200 khz 68 - 100 pf 15 - 30 pf 68 - 100 pf 15 - 30 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf higher capacitance increases the stability of the oscillator b ut also increases the star t-up time . these v alues are f or design guidance only . rs ma y be required in hs mode as w ell as xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci cation. since each cr ystal has its o wn char acter istics , the user should consult the cr ystal man u- f acturer f or appropr iate v alues of e xter nal components .
pic16c62x ds30235g -page 48 preliminary 1998 microchip technology inc. 9.2.3 e xternal cr ystal oscillator circuit either a prepac kaged oscillator can be used or a simple oscillator circuit with ttl gates can be b uilt. prepac kaged oscillators pro vide a wide oper ating r ange and better stability . a w ell-designed cr ystal oscillator will pro vide good perf or mance with ttl gates . t w o types of cr ystal oscillator circuits can be used; one with ser ies resonance , or one with par allel resonance . figure 9-4 sho ws implementation of a par allel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the cr ystal. the 74as04 in v er ter perf or ms the 180 phase shift that a par allel oscillator requires . the 4.7 k w resistor pro vides the negativ e f eedbac k f or stability . the 10 k w potentiometers bias the 74as04 in the linear region. this could be used f or e xter nal oscillator designs . figure 9-4: external p arallel resonant cr ystal oscillator cir cuit figure 9-5 sho ws a ser ies resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the cr ystal. the in v er ter perf or ms a 180 phase shift in a ser ies resonant oscillator circuit. the 33 0 k w resistors pro vide the negativ e f eedbac k to bias the in v er ters in their linear region. figure 9-5: external series resonant cr ystal osci l lator cir cuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xt al 10k 74as04 pic16c 62x clk in t o o ther de vices 330 k w 74as04 74as04 pic16c 62x clk in t o o ther de vices xt al 33 0 k w 74as04 0.1 m f 9.2.4 rc oscillator f or timing insensitiv e applications the ?c de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resistor (re xt) and capacitor (ce xt) v alues , and the oper ating temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal process par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w ce xt v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c components used. figure 9-6 sho ws ho w the r/c combination is connected to the pic16c 62x. f or re xt v alues belo w 2.2 k w , the oscillator oper ation ma y become unstab le , or stop completely . f or v er y high re xt v alues (e .g. , 1 m w ), the oscillator becomes sensitiv e to noise , humidity and leakage . thus , w e recommend to k eep re xt betw een 3 k w and 100 k w . although the oscillator will oper ate with no e xter nal capacitor (ce xt = 0 pf), w e recommend using v alues abo v e 20 pf f or noise and stability reasons . with no or small e xter nal capacitance , the oscillation frequency can v ar y dr amatically due to changes in e xter nal capacitances , such as pcb tr ace capacitance or pac kage lead fr ame capacitance . see section 13.0 f or rc frequency v ar iation from par t to par t due to nor mal process v ar iation. the v ar iation is larger f or larger r (since leakage current v ar iation will aff ect rc frequency more f or large r) and f or smaller c (since v ar iation of input capacitance will aff ect rc fre- quency more). see section 13.0 f or v ar iation of oscillator frequency due to v dd f or giv en re xt/ce xt v alues as w ell as frequency v ar iation due to oper ating temper ature f or giv en r, c , and v dd v alues . the oscillator frequency , divided b y 4, is a v ailab le on the osc2/clk out pin, and can be used f or test pur poses or to synchroniz e other logic ( figure 3-2 f or w a v ef or m). figure 9-6: rc oscillator mode osc2/clkout cext rext v dd pic16c 62x osc1 fosc/4 internal clock v dd
1998 microchip technology inc. preliminary ds30235g -page 49 pic16c62x 9.3 reset the pic16c62x d iff erentiates betw een v ar ious kinds of reset: a) p o w er-on reset (por) b) mclr reset dur ing nor mal oper ation c) mclr reset dur ing sleep d) wdt r eset (n or mal oper ation ) e) wdt w ak e-up ( sleep ) f) bro wn-out reset (bor) some registers are not aff ected in an y reset condition; their status is unkno wn on por and unchanged in an y other reset. most other registers are reset to a ?eset state on p o w er-on reset, mclr reset, wdt reset an d mclr reset dur ing sleep . the y are not aff ected b y a wdt w ak e-up , s ince this i s vie w ed as the resumption of nor mal oper ation. t o and pd bits are set or cleared diff erently in diff erent reset situations as indicated in t ab le 9-4 . these bits are used in softw are to deter mine the nature of the reset. see t ab le 9-7 f or a full descr ip- tion of reset states of all registers . a simpli ed b loc k diag r am of the on-chip reset circuit is sho wn in figure 9-7 . the mclr reset path has a noise lter to detect and ignore small pulses . see t ab le 12-6 f or pulse width speci cation. figure 9-7: simplified blo c k dia gr a m of on-c hip reset cir cuit s r q exter nal reset mclr / v dd osc1/ wdt module v dd r ise detect ost/pwr t on-chip (1) rc osc wdt time-out p o w er-on reset ost pwr t chip_reset 10 -b it ripple-counter r eset enab le ost enab le pwr t sleep see t ab le 9-3 f or time-out situations . note 1: this is a separ ate oscillator from the rc oscillator of the clkin pin. bro wn-out reset boren clkin pin v pp pin 10-bit ripple -c ounter q
pic16c62x ds30235g -page 50 preliminary 1998 microchip technology inc. 9.4 p o wer -on reset (por), p o wer -up timer (pwr t), oscillator star t-up timer (ost) and br o wn-out reset (bor) 9.4.1 p o w er-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough le v el f or proper oper a- tion. t o tak e adv antage of the por, just tie the mclr pin through a resistor to v dd . this will eliminate e xter- nal rc components usually needed to create p o w er- o n reset. a maxim um r ise time f or v dd is required. see electr ical speci cations f or details . the por circuit does not produce an inter nal reset when v dd declines . when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper ating par ameters (v oltage , frequency , temper ature , etc.) m ust be met to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met. f or additional inf or mation, ref er to application note an607 ? o w er-up t roub le shooting? 9.4.2 p o w er-up timer (pwr t) the p o w er- u p timer pro vides a x ed 72 ms (nominal) time-out on p o w er-up only , from por or bro wn-out reset . the p o w er-up t imer oper ates on an inter nal rc oscillator . the chip is k ept in reset as long as pwr t is activ e . the pwr t dela y allo ws the v dd to r ise to an acceptab le le v el. a con gur ation bit, pw r te can disab le (if set) or enab le (if cleared or prog r ammed) the p o w er-up t imer . the p o w er-up timer should alw a ys be enab led when bro wn-out reset is enab led. the p o w er-up time dela y will v ar y from chip to chip and due to v dd , temper ature and process v ar iation. see dc par ameters f or details . 9.4.3 oscillator star t-up timer (ost) the oscillator star t-up timer (ost) pro vides a 1024 oscillator cycle (from osc1 input) dela y after the pwr t dela y is o v er . this ensures that the cr ystal oscillator or resonator has star ted and stabiliz ed. the ost time-out is in v ok ed only f or xt , lp and hs modes and only on po w er-on reset or w ak e-up from sleep . 9.4.4 bro wn-out reset (bor) the pic16c62x members ha v e on-chip b ro wn-out reset circuitr y . a con gur ation bit, bo r en, can dis- ab le (if clear/prog r ammed) or enab le (if set) the bro wn-out r eset circuitr y . if v dd f alls belo w 4.0v ref er to v bor par ameter d 005 (v bor ) f or g reater than par ameter (tbor) i n t ab le 12-6 , the bro wn-out situa- tion will reset the chip . a reset is not guar anteed to occur if v dd f alls belo w 4.0v f or less than par ameter ( tbor ) . on an y reset (p o w er-on, bro wn-out, w atchdog, etc.) t he chip will remain in reset until v dd r ises abo v e bv dd . the p o w er- u p timer will no w be in v ok ed and will k eep the chip in reset an additional 72 ms . if v dd drops belo w bv dd while the p o w er- u p timer is r unning, the chip will go bac k into a bro wn-out r eset and the p o w er- u p timer will be re- initializ ed. once v dd r ises abo v e bv dd , the p o w er-up timer will e x ecute a 72 ms reset. the p o w er-up timer should alw a ys be enab led when bro wn-out reset is enab led. figure 9-8 sho ws typical bro wn-out situations . figure 9-8: br o wn-out situations 72 ms bv dd max. bv dd min. v dd inter nal reset bv dd max. bv dd min. v dd inter nal reset 72 ms <72 ms 72 ms bv dd max. bv dd min. v dd inter nal reset
1998 microchip technology inc. preliminary ds30235g -page 51 pic16c62x 9.4.5 time-out sequence on po w er-up the time-out sequence is as f ollo ws: first pwr t time-out is in v ok ed after por has e xpired. then ost is activ ated. the total time-out will v ar y based on oscillator con gur ation and p w r te bit status . f or e xample , in rc mode with pw r te bit er ased (pwr t disab led), there will be no time-out at all. figure 9-9 , figure 9-10 and figure 9-11 depict time-out sequences . since the time-outs occur from the por pulse , if mclr is k ept lo w long enough, the time-outs will e xpire . then br inging mclr high will begin e x ecution immediately (see figure 9-10 ). this is useful f or testing pur poses or to synchroniz e more than one pic16c62x de vice oper- ating in par allel. t ab le 9-6 sho ws the reset conditions f or some special registers , while t ab le 9-7 sho ws the reset conditions f or all the registers . 9.4.6 p o w er control (pcon)/ status register the po w er control/status register , pcon (address 8eh) has tw o bits . bit0 is bor (bro wn-out). bor is unkno wn on po w er-on-reset. it m ust then be set b y the user and chec k ed on subsequent resets to see if bor = 0 indicating that a bro wn-out has occurred. the bor status bit is a don? care and is not necessar ily predictab le if the bro wn-out circuit is disab led (b y setting bo r en bit = 0 in the con gur ation w ord). bit1 is por (p o w er-on-reset). it is a ? on po w er-on-reset and unaff ected otherwise . the user m ust wr ite a ? to this bit f ollo wing a po w er-on-reset. on a subsequent reset if por is ?? it will indicate that a po w er-on-reset m ust ha v e occurred (v dd ma y ha v e gone too lo w). t able 9-3: time-out in v arious situations t able 9-4: status /pcon bits and their significance legend: u = unchanged, x = unkno wn oscillator con guration p o wer -up br o wn-out reset w ake-up fr om sleep pwr te = 0 pwr te = 1 xt , hs , lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms 72 ms por bor t o pd 0 x 1 1 p o w er-on-reset 0 x 0 x illegal, t o is set on por 0 x x 0 illegal, pd is set on por 1 0 x x bro wn-out r eset 1 1 0 u wdt r eset 1 1 0 0 wdt w ak e - up 1 1 u u mclr reset dur ing nor mal oper ation 1 1 1 0 mclr reset dur ing sleep t able 9-5: summar y of register s associated with br o wn-out ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por reset v alue on all other resets (1) 83h st a tus t o pd 0001 1xxx 000q quuu 8eh pcon por bor ---- --0x ---- --uq note1: other (non po w er-up) resets include mclr reset, bro wn-out reset and w atchdog timer reset dur ing nor mal oper ation.
pic16c62x ds30235g -page 52 preliminary 1998 microchip technology inc. t able 9-6: initialization condition f or special register s t able 9-7: initialization condition f or register s condition pr ogram counter st a tus register pcon register p o w er - on r eset 000h 0001 1xxx ---- --0x mclr reset dur ing nor mal oper ation 000h 000u uuuu ---- --uu mclr reset dur ing sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 uuuu ---- --uu wdt w ak e-up pc + 1 uuu0 0uuu ---- --uu bro wn-out r eset 000h 000x xuuu ---- --u0 interr upt w ak e-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unkno wn, - = unimplemented bit, reads as ?? note 1: when the w ak e-up is due to an interr upt and global enab le bit, gie is set, the pc is loaded with the interr upt v ector (0004h) after e x ecution of pc+1. register ad dress p o wer -on reset mclr rese t during normal operation mclr rese t during sleep wdt reset br o wn-out r eset (1) w ake up fr om sleep thr ough interrupt w ake up fr om sleep thr ough wdt time-out w - xxxx xxxx uuuu uuuu uuuu uuuu indf 00h - - - tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000 0000 0000 0000 pc + 1 (3) st a tus 03h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu por t a 05h ---x xxxx ---u uuuu ---u uuuu por tb 06h xxxx xxxx uuuu uuuu uuuu uuuu cmcon 1fh 00-- 0000 00-- 0000 uu-- uuuu pcla th 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uqqq (2) pir1 0ch -0-- ---- -0-- ---- -q-- ---- (2,5) option 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu pie1 8ch -0-- ---- -0-- ---- -u-- ---- pcon 8eh ---- --0x ---- --uq (1,6) ---- --uu vrcon 9fh 000- 0000 000- 0000 uuu- uuuu legend: u = unchanged, x = unkno wn, - = unimplemented bit, reads as ?? q = v alue depends on condition. note 1: if v dd goes too lo w , p o w er-on reset will be activ ated and registers will be aff ected diff erently . 2: one or more bits in intcon, pir1 and/or pir2 will be aff ected (to cause w ak e-up). 3: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). 4: see t ab le 9-6 f or reset v alue f or speci c condition. 5: if w ak e-up w as due to compar ator input changing, then bit 6 = 1. all other interr upts gener ating a w ak e-up will cause bit 6 = u. 6: if reset w as due to bro wn-out, then bit 0 = 0. all other resets will cause bit 0 = u.
1998 microchip technology inc. preliminary ds30235g -page 53 pic16c62x figure 9-9: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 1 figure 9-10: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 2 figure 9-11: time-out sequence on p o wer -up ( mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
pic16c62x ds30235g -page 54 preliminary 1998 microchip technology inc. figure 9-12: external p o wer -on reset cir cuit (for slo w v dd p o wer -up) note 1: exter nal po w er-on reset circuit is required only if v dd po w er-up slope is too slo w . the diode d helps discharge the capaci- tor quic kly when v dd po w ers do wn. 2: < 40 k w is recommended to mak e sure that v oltage drop across r does not vio- late the de vice s electr ical speci cation. 3: r1 = 100 w to 1 k w will limit an y current o wing into mclr from e xter nal capaci- tor c in the e v ent of mclr / v pp pin break- do wn due to electrostatic discharge (esd) or electr ical ov erstress (eos). c r1 r d v dd mclr pic16c62x v dd figure 9-13: external br o wn-out pr otection cir c uit 1 figure 9-14: external br o w n -out pr otection cir c uit 2 note 1: this circuit will activ ate reset when v dd goes belo w (vz + 0.7v) where vz = zener v oltage . 2: inter nal bro wn-out reset circuitr y should be disab led when using this cir- cuit. v dd 33k 10k 40k v dd mclr pic16c62x note 1: this bro wn-out circuit is less e xpensiv e , albeit less accur ate . t r ansistor q1 tur ns off when v dd is belo w a cer tain le v el such that: 2: inter nal bro wn-out reset should be dis- ab led when using this circuit. 3: resistors should be adjusted f or the char acter istics of the tr ansistor . v dd x r1 r1 + r2 = 0.7 v v dd r2 40k v dd mclr pic16c62x r1 q1
1998 microchip technology inc. preliminary ds30235g -page 55 pic16c62x 9.5 interrupts the pic16c62x has 4 sources of interr upt: exter nal interr upt rb0/int tmr0 o v er o w interr upt p or tb change interr upts (pins rb7: rb 4) compar ator interr upt the interr upt control register (intcon) records individual interr upt requests in ag bits . it also has individual and global interr upt enab le bits . a global interr upt enab le bit, gie (intcon<7>) enab les (if set) all un-mask ed interr upts or disab les (if cleared) all interr upts . individual interr upts can be disab led through their corresponding enab le bits in intcon register . gie is cleared on reset. the ?etur n from interr upt instr uction, retfie , e xits interr upt routine as w ell as sets the gie bit, which re-enab le rb0/int interr upts . the int pin interr upt, the rb por t change interr upt and the tmr0 o v er o w interr upt ags are contained in the intcon register . the per ipher al interr upt ag is contained in the special register pir1. the corresponding interr upt enab le bit is contained in special registers pie1. when an interr upt is responded to , the gie is cleared to disab le an y fur ther interr upt, the retur n address is pushed into the stac k and the pc is loaded with 0004h. once in the interr upt ser vice routine the source(s) of the interr upt can be deter mined b y polling the interr upt ag bits . the interr upt ag bit(s) m ust be cleared in soft- w are bef ore re-enab ling interr upts to a v oid rb0/int recursiv e interr upts . f or e xter nal interr upt e v ents , such as the int pin or por tb change interr upt, the interr upt latency will be three or f our instr uction cycles . the e xact latency depends when the interr upt e v ent occurs ( figure 9-16 ). the latency is the same f or one or tw o cycle instr uctions . once in the interr upt ser vice routine the source(s) of the interr upt can be deter mined b y polling the interr upt ag bits . the interr upt ag bit(s) m ust be cleared in softw are bef ore re-enab ling interr upts to a v oid m ultiple interr upt requests . individual interr upt ag bits are set regardless of the status of their corresponding mask bit or the gie bit. note 1: individual interr upt ag bits are set regardless of the status of their corresponding mask bit or the gie bit. 2: wh en an instr uction that clears the gie bit is e x ecuted, an y interr upts that w ere pending f or e x ecution in the ne xt cycle are ignored. the cpu will e x ecute a nop in the cycle immediately f ollo wing the instr uction which clears the gie bit. the interr upts which w ere ignored are still pending to be ser viced when the gie bit is set again. figure 9-15: interrupt logic rbif rbie t0if t0ie intf inte gie peie w ak e-up (if in sleep mode) interr upt to cpu cmie cmif
pic16c62x ds30235g -page 56 preliminary 1998 microchip technology inc. 9.5.1 rb0/int interr upt exter nal interr upt on rb0/int pin is edge tr iggered: either r ising if intedg bit (option<6>) is set, or f all- ing, if intedg bit is clear . when a v alid edge appears on the rb0/ int pin, the intf bit (intcon<1>) is set. this interr upt can be disab led b y clear ing the inte control bit (intcon<4>). the intf bit m ust be cleared in softw are in the interr upt ser vice routine bef ore re-enab ling this interr upt. the rb0/ int interr upt can w ak e - up the processor from sleep , if the inte bit w as set pr ior to going into sleep . the status of the gie bit decides whether or not the processor br anches to the interr upt v ector f ollo wing w ak e-up . see section 9.8 f or details on sleep and figure 9-18 f or timing of w ak e-up from sleep through rb0/ int interr upt. 9.5.2 tmr0 interr upt an o v er o w (ffh ? 00h) in the tmr0 r e gister will set the t0if (intcon<2>) bit. the interr upt can be enab led/disab led b y setting/clear ing t0ie (intcon<5>) bit. f or oper ation of the tim e r0 module , see section 6.0 . 9.5.3 p or tb interr upt an input change on p or tb <7:4> sets the rbif (intcon<0>) bit. the interr upt can be enab led/dis- ab led b y setting/clear ing the rbie (intcon<4>) bit. f or oper ation of p or tb ( section 5.2 ) . 9.5.4 compar ator interr upt see section 7.6 f or complete descr iption of compar ator interr upts . note: if a change on the i/o pin should occur when the read oper ation is being e x ecuted (star t of the q2 cycle), then the rbif inter- r upt ag ma y not get set. figure 9-16: int pin interrupt timing t able 9-8: summar y of interrupt register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por reset v alue on all other resets (1) 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 cmif -0-- ---- -0-- ---- 8ch pie1 cmie -0-- ---- -0-- ---- note1: other (non po w er-up) resets include mclr reset, bro wn-out reset and w atchdog timer reset dur ing nor mal oper ation. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clk out int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted interr upt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dumm y cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dumm y cycle inst (pc) 1 4 5 1 note 1: intf ag is sampled here (e v er y q1). 2: asynchronous interr upt latency = 3-4 tcy . synchronous latency = 3 tcy , where tcy = instr uction cycle time . latency is the same whether inst (pc) is a single cycle or a 2-cycle instr uction. 3: clk out is a v ailab le only in rc oscillator mode . 4: f or minim um width of int pulse , ref er to a c specs . 5: intf is enab led to be set an ytime dur ing the q4-q1 cycles . 2 3
1998 microchip technology inc. preliminary ds30235g -page 57 pic16c62x 9.6 conte xt sa ving during interrupts dur ing an interr upt, only the retur n pc v alue is sa v ed on the stac k. t ypically , users ma y wish to sa v e k e y reg- isters dur ing an interr upt e .g. w register and st a tus register . this will ha v e to be implemented in softw are . example 9-1 stores and restores the st a tus and w registers . the user register , w_temp , m ust be de ned in both banks and m ust be de ned at the same offset from the bank base address (i.e . , w_temp is de ned at 0x20 in bank 0 and it m ust also be de ned at 0xa0 in bank 1). the user register , st a tus_temp , m ust be de ned in bank 0. the example 9-1 : stores the w register stores the st a tus register in bank 0 ex ecutes the isr code restores the st a tus (and bank select bit register) restores the w register example 9-1: sa ving the status and w register s in ram movwf w_temp ;copy w to temp register, ;could be in either bank swapf status,w ;swap status to be saved into w bcf status,rp0 ;change to bank 0 regardless ;of current bank movwf status_temp ;save status to bank 0 ;register : : (isr) : swapf status_temp,w ;swap status_temp register ;into w, sets bank to original ;state movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w 9.7 w atc hdog timer (wdt) the w atchdog timer is a free r unning on-chip rc oscil- lator which does not require an y e xter nal components . this rc oscillator is separ ate from the rc oscillator of the clkin pin. that means that the wdt will r un, e v en if the cloc k on the osc1 and osc2 pins of the de vice has been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur ing nor mal oper ation, a wdt time-out gener ates a de vice reset . if the de vice is in sleep mode , a wdt time - out causes the de vice to w ak e-up and contin ue with nor mal oper ation. the wdt can be per manently disab led b y prog r amming the con- gur ation bit wdte as clear ( section 9.1 ). 9.7.1 wdt p er iod the wdt has a nominal time-out per iod of 18 ms , (with no prescaler). the time-out per iods v ar y with temper a- ture , v dd and process v ar iations from par t to par t (see dc specs). if longer time-out per iods are desired, a prescaler with a division r atio of up to 1:128 can be assigned to the wdt under softw are control b y wr iting to the option register . thus , time-out per iods up to 2.3 seconds can be realiz ed. the clrwdt and sleep instr uctions clear the wdt and the postscaler , if assigned to the wdt , and pre v ent it from timing out and gener ating a de vice reset . the t o bit in the st a tus register will be cleared upon a w atchdog t imer time-out. 9.7.2 wdt prog r amming consider ations it should also be tak en in account that under w orst case conditions ( v dd = min., t emper ature = max., max. wdt prescaler) it ma y tak e se v er al seconds bef ore a wdt time-out occurs .
pic16c62x ds30235g -page 58 preliminary 1998 microchip technology inc. figure 9-17: w atc hdog timer bloc k dia gram t able 9-9: summar y of w atc hdog timer register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con g. bits --- bo r en cp1 cp0 pwr te wdte fosc1 fosc0 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used b y the w atchdog timer . note: _ = unimplemented location, read as ? + = reser v ed f or future use f rom tmr0 cloc k source ( figure 6-6 ) t o tmr0 ( figure 6-6 ) p ostscaler w atchdog timer m u x psa 8 - to -1 mux psa wdt time-out 1 0 0 1 wdt enab le bit ps <2: 0 > note: t0se, t0cs , psa, ps0-ps2 are bits in the option register . 8 mux
1998 microchip technology inc. preliminary ds30235g -page 59 pic16c62x 9.8 p o wer -do wn mode (sleep) the p o w er- d o wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the pd bit in the st a tus register is cleared, the t o bit is set, and the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had, bef ore sleep w as e x ecuted (dr iving high, lo w , or hi-impedance). f or lo w est current consumption in this mode , all i/o pins should be either at v dd , or v ss , with no e xter nal circuitr y dr a wing current from the i/o pin and the com- par ators and v ref should be disab led. i/o pins that are hi-impedance inputs should be pulled high or lo w e xter- nally to a v oid s witching currents caused b y oating inputs . the t0cki input should also be at v dd or v ss f or lo w est current consumption. the contr ib ution from on chip pull-ups on p or tb should be considered. the mclr pin m ust be at a logic high le v el ( v ihmc ). 9.8.1 w ak e-up from sleep the de vice can w ak e - up from sleep through one of the f ollo wing e v ents: 1. exter nal reset input on mclr pin 2. w atchdog t imer w ak e-up (if wdt w as enab led) 3. interr upt from rb0/ int pin, rb p or t change , or the p er ipher al interr upt (compar ator). the rst e v ent will cause a de vice reset. the tw o latter e v ents are considered a contin uation of prog r am e x e- cution. the t o and pd bits in the st a tus register can be used to deter mine the cause of de vice reset. pd bit, which is set on po w er-up is cleared when sleep is in v ok ed. t o bit is cleared if wdt w ak e-up occurred. when the sleep instr uction is being e x ecuted, the ne xt instr uction (pc + 1) is pre-f etched. f or the de vice to w ak e-up through an interr upt e v ent, the correspond- ing interr upt enab le bit m ust be set (enab led). w ak e-up is regardless of the state of the gie bit. if the gie bit is clear (disab led), the de vice contin ues e x ecution at the instr uction after the sleep instr uction. if the gie bit is set (enab led), the de vice e x ecutes the instr uction after the sleep instr uction and then br anches to the inter- r upt address (0004h). in cases where the e x ecution of the instr uction f ollo wing sleep is not desir ab le , the user should ha v e a n nop a fter the sleep instr uction. the wdt is cleared when the de vice w ak es-up from sleep , regardless of the source of w ak e-up . note: it should be noted that a reset gener ated b y a wdt time-out does not dr iv e mclr pin lo w . note: if the global interr upts are disab led (gie is cleared), b ut an y interr upt source has both its interr upt enab le bit and the correspond- ing interr upt ag bits set, the de vice will immediately w ak eup from sleep . the sleep instr uction is completely e x ecuted. figure 9-18: w ake-up fr om sleep thr ough interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clk out(4) int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interr upt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dumm y cycle pc + 2 0004h 0005h dumm y cycle t ost (2) pc+2 note 1: xt , hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (dr a wing not to scale) this dela y will not be there f or rc osc mode . 3: gie = '1' assumed. in this case after w ak e- up , the processor jumps to the interr upt routine . if gie = '0', e x ecution will contin ue in-line . 4: clk out is not a v ailab le in these osc modes , b ut sho wn here f or timing ref erence .
pic16c62x ds30235g -page 60 preliminary 1998 microchip technology inc. 9.9 code pr otection if the code protection bit(s) ha v e not been prog r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . 9.10 id locations f our memor y locations (2000h-2003h) are designated as id locations where the user can store chec ksum or other code-identi cation n umbers . these locations are not accessib le dur ing nor mal e x ecution b ut are readab le and wr itab le dur ing prog r am/v er ify . only the least signi cant 4 bits of the id locations are used . note: microchip does not recommend code protecting windo w ed de vices . 9.11 in-cir cuit serial pr ogramming the pic16c62x m icrocontrollers can be ser ially prog r ammed while in the end application circuit. this is simply done with tw o lines f or cloc k and data, and three other lines f or po w er , g round, and the prog r amming v oltage . this allo ws customers to man uf acture boards with unprog r ammed de vices , and then prog r am the microcontroller just bef ore shipping the product. this also allo ws the most recent r mw are or a custom r mw are to be prog r ammed. the de vice is placed into a prog r am/v er ify mode b y holding the rb6 and rb7 pins lo w while r aising the mclr ( v pp ) pin from v il to v ihh ( see prog r amming speci cation). rb6 becomes the prog r amming cloc k and rb7 becomes the prog r amming data. both rb6 and rb7 are schmitt t r igger inputs in this mode . after reset, to place the de vice into prog r amming/v er ify mode , the prog r am counter (pc) is at location 00h. a 6-bit command is then supplied to the de vice . depending on the command, 14-bits of prog r am data are then supplied to or from the de vice , depending if the command w as a load or a read. f or complete details of ser ial prog r amming, please ref er to the pic16c6x/7x /9xx prog r amming speci cations (#ds30228). a typical in- circuit ser ial prog r amming connection is sho wn in figure 9-19 . figure 9-19: t ypic a l in- cir cuit serial pr o gramming connection exter nal connector signals t o nor mal connections t o nor mal connections pic16c 62x v dd v ss mclr / v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
1998 microchip technology inc. preliminary ds30235g -page 61 pic16c62x 10.0 inst ruction set summar y each pic16c62x i nstr uction is a 14-bit w ord divided into an opcode which speci es the instr uction type and one or more oper ands which fur ther specify the oper ation of the instr uction. the pic16c62x i nstr uc- tion set summar y in t ab le 10-2 lists b yte-oriented , bit- oriented , and literal and contr ol oper ations . t ab le 10-1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le register designator and 'd' represents a destination designator . the le register designator speci es which le register is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' is z ero , the result is placed in the w register . if 'd' is one , the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an eight or ele v en bit constant or liter al v alue . t ab le 10-1: opcode field descriptions field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8 -b it le register k liter al eld, constant data or label x don't care location (= 0 or 1) t he assemb ler will gener ate code with x = 0 . it is the recommended f or m of use f or c ompatibility with all microchip softw are tools . d destination select; d = 0: store result in w , d = 1: store result in le register f . def ault is d = 1 label label name tos t op of stac k pc prog r am counter pclath prog r am counter high latch gie global interr upt enab le bi t wdt w atchdog timer /c ounter to time-out bi t pd p o w er-do wn bi t dest destination either the w register or the s peci ed register le location [ ] options ( ) contents ? assigned to < > register bit eld ? in the set of i talics user de ned ter m (f ont is cour ier) the instr uction set is highly or thogonal and is g rouped into three basic categor ies: byte -o riented oper ations bit -o riented oper ations literal and contr ol oper ations all instr uctions are e x ecuted within one single instr uction cycle , unless a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles with the second cycle e x ecuted as a nop . one instr uction cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction, the instr uction e x ecution time is 2 m s . t ab le 10-1 l ists the instr uctions recogniz ed b y the mp asm assemb ler . figure 10-1 sho ws the three gener al f or mats that the instr uctions can ha v e . all e xamples use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh where h signi es a he xadecimal digit. figure 10-1: general format f or instructions note: t o maintain upw ard c ompatibility with future pic micro p roducts , do not use the option and tris instr uctions . byte-oriented le register oper ations 13 8 7 6 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 7-bit le register address bit-oriented le register oper ations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit le register address literal and contr ol oper ations 13 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue 13 11 10 0 opcode k ( liter al) k = 11-bit immediate v alue gener al call and goto instr uctions only
pic16c62x ds30235g -page 62 preliminary 1998 microchip technology inc. t ab le 10-2: pic16c62x instruction set mnemonic, operands description cyc les 14-bit opcode status aff ected notes ms b ls b byte-oriented file register opera tions add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f , d f , d f - f , d f , d f , d f , d f , d f , d f , d f - f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate right f through carr y subtr act w from f sw ap nib b les in f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z z z z c c c ,dc ,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and contr ol opera tions addl w andl w call clr wdt go t o iorl w mo vl w retfie retl w return sleep subl w xorl w k k k - k k k - k - - k k add liter al and w and liter al with w call subroutine clear w atchdog time r go to address inclusiv e or liter al with w mo v e liter al to w retur n from interr upt retur n with liter al in w retur n from subroutine go into standb y mode subtr act w from liter al exc lusiv e o r liter al with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c ,dc ,z z t o , pd z t o , pd c ,dc ,z z note 1: when an i/o register is modi ed as a function of itself ( e .g. , movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 2: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared if assigned to the timer0 module . 3: if prog r am counter (pc) is modi ed or a conditional test is tr ue , the instr uction requires tw o cycles . t he second cycle is e x ecuted as a nop .
1998 microchip technology inc. preliminary ds30235g -page 63 pic16c62x 10.1 instruction descriptions addl w ad d literal and w syntax: [ label ] a ddl w k oper ands: 0 k 255 oper ation: (w) + k ? ( w ) status aff ected: c , dc , z encoding: 11 111x kkkk kkkk descr iption: the contents of the w register are added to the eight bit liter al 'k' a nd the result is placed in the w register . w ords: 1 cycles: 1 example addlw 0x15 bef ore instr uction w = 0x10 after instr uction w = 0x25 add wf ad d w and f syntax: [ label ] add wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) + (f) ? (dest) status aff ected: c , dc , z encoding: 00 0111 dfff ffff descr iption: add the contents of the w register with r egister 'f'. i f 'd' i s 0 the result is stored in the w register . i f 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example addwf fsr, 0 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0xd9 fsr = 0xc2 andl w and literal with w syntax: [ label ] a ndl w k oper ands: 0 k 255 oper ation: (w) .and . (k) ? ( w ) status aff ected: z encoding: 11 1001 kkkk kkkk descr iption: the contents of w register are and?d with the eight bit liter al 'k'. t he result is placed in the w register . w ords: 1 cycles: 1 example andlw 0x5f bef ore instr uction w = 0xa3 after instr uction w = 0x03 and wf and w with f syntax: [ label ] a nd wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .and . (f) ? (dest) status aff ected: z encoding: 00 0101 dfff ffff descr iption: and the w register with register 'f'. i f 'd' i s 0 the result is stored in the w register . i f 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example andwf fsr, 1 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0x17 fsr = 0x02
pic16c62x ds30235g -page 64 preliminary 1998 microchip technology inc. bcf bit clear f syntax: [ label ] b cf f ,b oper ands: 0 f 127 0 b 7 oper ation: 0 ? ( f < b> ) status aff ected: none encoding: 01 00bb bfff ffff descr iption: bit 'b' i n register 'f' i s cleared . w ords: 1 cycles: 1 example bcf flag_reg, 7 bef ore instr uction fla g_reg = 0xc7 after instr uction fla g_reg = 0x47 bsf bit set f syntax: [ label ] b sf f ,b oper ands: 0 f 127 0 b 7 oper ation: 1 ? ( f ) status aff ected: none encoding: 01 01bb bfff ffff descr iption: bit 'b' i n register 'f' i s set. w ords: 1 cycles: 1 example bsf flag_reg, 7 bef ore instr uction fla g_reg = 0x0a after instr uction fla g_reg = 0x8a btfsc b it t est, sk ip if clear syntax: [ label ] b tfsc f ,b oper ands: 0 f 127 0 b 7 oper ation: skip if (f) = 0 status aff ected: none encoding: 0 1 10bb bfff ffff descr iption: if bit ' b' in register ' f' is '0' then the ne xt i nstr uction is skipped. if bit 'b' i s '0' t hen the ne xt instr uction f etched dur ing the current instr uction e x ecution i s discarded , and a nop is e x ecuted instead, making this a tw o-cycle instr uction . w ords: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address true if fla g<1>= 1, pc = address f alse
1998 microchip technology inc. preliminary ds30235g -page 65 pic16c62x btfss bit t est f , sk ip if set syntax: [ label ] b tfss f ,b oper ands: 0 f 127 0 b < 7 oper ation: skip if (f) = 1 status aff ected: none encoding: 01 11bb bfff ffff descr iption: if bit 'b' i n register 'f' i s '1' t hen the ne xt instr uction is skipped. if bit 'b' i s '1', then the ne xt instr uction f etched dur ing the current instr uction e x ecution, is discarded and a nop is e x ecuted instead, making this a tw o-cycle instr uction. w ords: 1 cycles: 1(2) example here false true btfss goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address f alse if fla g<1> = 1, pc = address t rue call call subr outine syntax: [ label ] call k oper ands: 0 k 2047 oper ation: (pc)+ 1 ? t os , k ? pc<10:0>, (pcla th<4:3>) ? pc<12:11> status aff ected: none encoding: 10 0kkk kkkk kkkk descr iption: call subroutine . first, retur n address (pc+1) is pushed onto the stac k. the ele v en bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pcla th. call is a tw o-cycle instr uction. w ords: 1 cycles: 2 example here call there bef ore instr uction pc = a ddress h ere after instr uction pc = a ddress t here t os = a ddress h ere+1 clrf clear f syntax: [ label ] clrf f oper ands: 0 f 127 oper ation: 00h ? ( f ) 1 ? z status aff ected: z encoding: 00 0001 1fff ffff descr iption: the contents of register 'f' a re cleared and the z bit is set. w ords: 1 cycles: 1 example clrf flag_reg bef ore instr uction fla g_reg = 0x5a after instr uction fla g_reg = 0x00 z = 1 clr w clear w syntax: [ label ] clr w oper ands: none oper ation: 00h ? (w) 1 ? z status aff ected: z encoding: 00 0001 0000 0011 descr iption: w register i s cleared. zero bit (z) is set. w ords: 1 cycles: 1 example clrw bef ore instr uction w = 0x5a after instr uction w = 0x00 z = 1
pic16c62x ds30235g -page 66 preliminary 1998 microchip technology inc. clr wdt clear w atc hdog timer syntax: [ label ] clr wdt oper ands: none oper ation: 00h ? wdt 0 ? wdt prescaler , 1 ? t o 1 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0100 descr iption: clrwdt instr uction resets the w atchdog tim er . it also resets the prescaler of the wdt . status bits t o and pd are set. w ords: 1 cycles: 1 example clrwdt bef ore instr uction wdt counter = ? after instr uction wdt counter = 0x00 wdt prescale r = 0 t o = 1 pd = 1 comf complement f syntax: [ label ] comf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f ) ? (dest) status aff ected: z encoding: 00 1001 dfff ffff descr iption: the contents of register 'f' are complemented. if 'd' is 0 the result is stored in w . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example comf reg1,0 bef ore instr uction reg1 = 0x13 after instr uction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? (dest) status aff ected: z encoding: 00 0011 dfff ffff descr iption: decrement register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example decf cnt, 1 bef ore instr uction cnt = 0x01 z = 0 after instr uction cnt = 0x00 z = 1 decfsz decrement f , sk ip if 0 syntax: [ label ] decfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? ( d est) ; skip if result = 0 status aff ected: none encoding: 00 1011 dfff ffff descr iption: the contents of register 'f' are decremented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. i f the result is 0, the ne xt instr uction, which is already f etched, is discarded. a nop is e x ecuted instead making it a tw o-cycle instr uction. w ords: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
1998 microchip technology inc. preliminary ds30235g -page 67 pic16c62x go t o unconditional branc h syntax: [ label ] go t o k oper ands: 0 k 2047 oper ation: k ? pc<10:0> p cla th<4:3> ? pc<12:11> status aff ected: none encoding: 10 1kkk kkkk kkkk descr iption: goto is an unconditional br anch. the ele v en bit immediate v alue is loaded into pc bits <10:0>. the upper bits of pc are loaded from pcla th<4:3>. goto is a tw o-cycle instr uction. w ords: 1 cycles: 2 example goto there after instr uction pc = address there incf increment f syntax: [ label ] incf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest) status aff ected: z encoding: 00 1010 dfff ffff descr iption: the contents of register 'f' a re incremented. if 'd' i s 0 the result is placed in the w register . if 'd' i s 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example incf cnt, 1 bef ore instr uction cnt = 0xff z = 0 after instr uction cnt = 0x00 z = 1 incfsz increment f , sk ip if 0 syntax: [ label ] incfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest), skip if result = 0 status aff ected: none encoding: 00 1111 dfff ffff descr iption: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, the ne xt instr uction, which is already f etched, is discarded. a nop is e x ecuted instead making it a tw o-cycle instr uction . w ords: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorl w inc lusive or literal with w syntax: [ label ] iorl w k oper ands: 0 k 255 oper ation: (w) .or. k ? (w) status aff ected: z encoding: 11 1000 kkkk kkkk descr iption: the contents of the w register is o r?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example iorlw 0x35 bef ore instr uction w = 0x9a after instr uction w = 0xbf z = 1
pic16c62x ds30235g -page 68 preliminary 1998 microchip technology inc. ior wf inc lusive or w with f syntax: [ label ] ior wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .or. (f) ? ( dest) status aff ected: z encoding: 00 0100 dfff ffff descr iption: inclusiv e or the w register with register 'f'. if 'd' i s 0 the result is placed in the w register . if 'd' i s 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example iorwf result, 0 bef ore instr uction resul t = 0x13 w = 0x91 after instr uction resul t = 0x13 w = 0x93 z = 1 mo vl w mo ve literal to w syntax: [ label ] mo vl w k oper ands: 0 k 255 oper ation: k ? (w) status aff ected: none encoding: 11 00 xx kkkk kkkk descr iption: the eight bit liter al 'k' i s loaded into w register . t he don? cares will assemb le as 0 s . w ords: 1 cycles: 1 example movlw 0x5a after instr uction w = 0x5a mo vf mo ve f syntax: [ label ] mo vf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) ? (dest) status aff ected: z encoding: 00 1000 dfff ffff descr iption: the contents of register f is mo v ed to a destination dependent upon the status of d. if d = 0, destination is w register . if d = 1, the destination is le register f itself . d = 1 is useful to test a le register since status ag z is aff ected. w ords: 1 cycles: 1 example movf fsr, 0 after instr uction w = v alue in fsr register z = 1 mo vwf mo ve w to f syntax: [ label ] mo vwf f oper ands: 0 f 127 oper ation: (w) ? (f) status aff ected: none encoding: 00 0000 1fff ffff descr iption: mo v e data from w register to register 'f' . w ords: 1 cycles: 1 example movwf option bef ore instr uction option = 0xff w = 0x4f after instr uction option = 0x4f w = 0x4f
1998 microchip technology inc. preliminary ds30235g -page 69 pic16c62x nop no operation syntax: [ label ] nop oper ands: none oper ation: no oper ation status aff ected: none encoding: 00 0000 0xx0 0000 descr iption: no oper ation. w ords: 1 cycles: 1 example nop option load option register syntax: [ label ] option oper ands: none oper ation: ( w ) ? option status aff ected: none encoding: 00 0000 0110 0010 descr iption: the contents of the w register are loaded in the option register . this instr uction is suppor ted f or code compatibility with pic16c5x products . since option is a readab le/wr itab le register , the user can directly address it. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic micr o p r oducts, do not use this instruction. retfie return fr om interrupt syntax: [ label ] retfie oper ands: none oper ation: t os ? pc , 1 ? gie status aff ected: none encoding: 00 0000 0000 1001 descr iption: retur n from interr upt. stac k is pop ed and t op of stac k (t os) is loaded in the pc . interr upts are enab led b y setting g lobal interr upt enab le bit, g ie ( intcon<7>). this is a tw o-cycle instr uction. w ords: 1 cycles: 2 example retfie after interr upt pc = t os gie = 1 retl w return with literal in w syntax: [ label ] retl w k oper ands: 0 k 255 oper ation: k ? ( w ); t os ? pc status aff ected: none encoding: 11 01xx kkkk kkkk descr iption: the w register is loaded with the eight bit liter al 'k'. the prog r am counter is loaded from the top of the stac k (the retur n address). this is a tw o-cycle instr uction. w ords: 1 cycles: 2 example table call table ; w contains table ;offset value ? ;w now has table value addwf pc ; w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table bef ore instr uction w = 0x07 after instr uction w = v alue of k 8
pic16c62x ds30235g -page 70 preliminary 1998 microchip technology inc. return return fr om subr outine syntax: [ label ] return oper ands: none oper ation: t os ? pc status aff ected: none encoding: 00 0000 0000 1000 descr iption: retur n from subroutine . the stac k is pop e d and the top of the stac k (t os) is loaded into the prog r am counter . this is a tw o cycle instr uction. w ords: 1 cycles: 2 example return after interr upt pc = t os rlf rotate left f thr ough carr y syntax: [ label ] rlf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption b elo w status aff ected: c encoding: 00 1101 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the left through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is stored bac k in register 'f ' . w ords: 1 cycles: 1 example rlf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 1100 1100 c = 1 register f c rrf rotate right f thr ough carr y syntax: [ label ] rrf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption b elo w status aff ected: c encoding: 00 1100 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the r ight through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd ' is 1 the result is placed bac k in register 'f' . w ords: 1 cycles: 1 example rrf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 0111 0011 c = 0 sleep syntax: [ label ] sleep oper ands: none oper ation: 00h ? wdt , 0 ? wdt prescaler , 1 ? t o , 0 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0011 descr iption: the po w er -d o wn status bit , p d i s cleared. time-out status bit , t o i s set. w atchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 9.8 f or more details . w ords: 1 cycles: 1 example: sleep register f c
1998 microchip technology inc. preliminary ds30235g -page 71 pic16c62x subl w subtract w fr om literal syntax: [ label ] subl w k oper ands: 0 k 255 oper ation: k - (w) ? ( w) status aff ected: c , dc , z encoding: 11 110x kkkk kkkk descr iption: the w register is subtr acted (2 s com- plement method) from the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example 1: sublw 0x02 bef ore instr uction w = 1 c = ? after instr uction w = 1 c = 1; result is posi- tiv e example 2: bef ore instr uction w = 2 c = ? after instr uction w = 0 c = 1; result is z ero example 3: bef ore instr uction w = 3 c = ? after instr uction w = 0x ff c = 0; result is nega- tiv e subwf subtract w fr om f syntax: [ label ] subwf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f ) - (w) ? ( dest) status aff ected: c , dc , z encoding: 00 0010 dfff ffff descr iption: subtr act (2 s complement method ) w register from register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example 1: subwf reg1,1 bef ore instr uction reg1 = 3 w = 2 c = ? after instr uction reg1 = 1 w = 2 c = 1; result is positiv e example 2: bef ore instr uction reg1 = 2 w = 2 c = ? after instr uction reg1 = 0 w = 2 c = 1; result is z ero example 3: bef ore instr uction reg1 = 1 w = 2 c = ? after instr uction reg1 = 0x ff w = 2 c = 0; result is negativ e
pic16c62x ds30235g -page 72 preliminary 1998 microchip technology inc. sw apf swap nibb les in f syntax: [ label ] sw apf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f< 3:0>) ? ( d est < 7:4>) , ( f< 7:4>) ? ( d est < 3:0>) status aff ected: none encoding: 00 1110 dfff ffff descr iption: the upper and lo w er nib b les of register 'f' are e xchanged. if 'd' is 0 the result is placed in w register . if 'd' is 1 the result is placed in register 'f'. w ords: 1 cycles: 1 example swapf reg, 0 bef ore instr uction reg1 = 0xa5 after instr uction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f oper ands: 5 f 7 oper ation: ( w ) ? tris register f; status aff ected: none encoding: 00 0000 0110 0fff descr iption: the instr uction is suppor ted f or code compatibility with the pic16c5x products . since tris registers are readab le and wr itab le , the user can directly address them. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic micr o p r oducts, do not use this instruction. xorl w exc lusive or literal with w syntax: [ label ] xorl w k oper ands: 0 k 255 oper ation: (w) .xor. k ? ( w) status aff ected: z encoding: 11 1010 kkkk kkkk descr iption: the contents of the w register are xor?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: xorlw 0xaf bef ore instr uction w = 0xb5 after instr uction w = 0x1a xor wf exc lusive or w with f syntax: [ label ] xor wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .xor. (f) ? ( dest) status aff ected: z encoding: 00 0110 dfff ffff descr iption: exclusiv e or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example xorwf reg 1 bef ore instr uction reg = 0xaf w = 0xb5 after instr uction reg = 0x1a w = 0xb5
1998 microchip technology inc. preliminary ds30235g -page 73 pic16c62x 11.0 de velopment suppor t 11.1 de velopme nt t ools the picmicr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: mplab-ice real-time in-circuit em ulator icepic ? lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer simice picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c17 (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) k ee l oq ? ev aluation kits and prog r ammer 11.2 mplab-ice: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the mplab-ice univ ersal in-circuit em ulator is intended to pro vide the product de v elopment engineer with a complete microcontroller design tool set f or picmicro microcontrollers (mcus). mplab-ice is sup- plied with the mplab integ r ated de v elopment en viron- ment (ide), which allo ws editing, ?ak e and do wnload, and source deb ugging from a single en vi- ronment. interchangeab le processor modules allo w the system to be easily recon gured f or em ulation of diff erent pro- cessors . the univ ersal architecture of the mplab-ice allo ws e xpansion to suppor t all ne w microchip micro- controllers . the mplab-ice em ulator system has been designed as a real-time em ulation system with adv anced f ea- tures that are gener ally f ound on more e xpensiv e de v elopment tools . the pc compatib le 386 (and higher) machine platf or m and microsoft win do ws a 3.x or windo ws 95 en vironment w ere chosen to best mak e these f eatures a v ailab le to y ou, the end user . mplab-ice is a v ailab le in tw o v ersions . mplab- ice 1000 is a basic , lo w-cost em ulator system with simple tr ace capabilities . it shares processor mod- ules with the mplab-ice 2000. this is a full-f eatured em ulator system with enhanced tr ace , tr igger , and data monitor ing f eatures . both systems will oper ate across the entire oper ating speed reange of the picmicro mcu . 11.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a lo w-cost in-circuit em ulator solution f or the microchip pic12cxxx, pic16c5x and pic16cxxx f amilies of 8-bit o tp microcontrollers . icepic is designed to oper ate on pc-compatib le machines r anging from 386 through p entium ? based machines under windo ws 3.x, windo ws 95, or win- do ws nt en vironment. icepic f eatures real time , non- intr usiv e em ulation. 11.4 pr o ma te ii: univer sal pr ogrammer the pr o ma te ii univ ersal prog r ammer is a full-f ea- tured prog r ammer capab le of oper ating in stand-alone mode as w ell as pc-hosted mode . pr o ma te ii is ce compliant. the pr o ma te ii has prog r ammab le v dd and v pp supplies which allo ws it to v er ify prog r ammed memor y at v dd min and v dd max f or maxim um reliability . it has an lcd displa y f or displa ying error messages , k e ys to enter commands and a modular detachab le soc k et assemb ly to suppor t v ar ious pac kage types . in stand- alone mode the pr o ma te ii can read, v er ify or pro- g r am pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices . it can also set con gur ation and code-protect bits in this mode . 11.5 picst ar t plus entr y le vel de velopment system the picst ar t prog r ammer is an easy-to-use , lo w- cost prototype prog r ammer . it connects to the pc via one of the com (rs-232) por ts . mplab integ r ated de v elopment en vironment softw are mak es using the prog r ammer simple and ef cient. picst ar t plus is not recommended f or production prog r amming. picst ar t plus suppor ts all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices with up to 40 pins . larger pin count de vices such as the pic16c923, pic16c924 and pic17c756 ma y be sup- por ted with an adapter soc k et. picst ar t plus is ce compliant.
pic16c62x ds30235g -page 74 preliminary 1998 microchip technology inc. 11.6 simice entr y-le vel har d ware sim ulator simice is an entr y-le v el hardw are de v elopment sys- tem designed to oper ate in a pc-based en vironment with microchip s sim ulator mplab-sim. both sim- ice and mplab-sim r un under microchip t echnol- ogy s mplab integ r ated de v elopment en vironment (ide) softw are . speci cally , simice pro vides hardw are sim ulation f or microchip s pic12c5xx, pic12ce5xx, and pic16c5x f amilies of picmicro 8-bit microcon- trollers . simice w or ks in conjunction with mplab-sim to pro vide non-real-time i/o por t em ulation. simice enab les a de v eloper to r un sim ulator code f or dr iving the target system. in addition, the target system can pro vide input to the sim ulator code . this capability allo ws f or simple and inter activ e deb ugging without ha ving to man ually gener ate mplab-sim stim ulus les . simice is a v aluab le deb ugging tool f or entr y- le v el system de v elopment. 11.7 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstr ates the capabilities of se v er al of microchip s microcontrol- lers . the microcontrollers suppor ted are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessar y hardw are and softw are is included to r un basic demo prog r ams . the users can prog r am the sample micro controllers pro vided with the picdem-1 board, on a pr o ma te ii or picst ar t -plus prog r ammer , and easily test r m- w are . the user can also connect the picdem-1 board to the mplab-ice em ulator and do wn load the r mw are to the em ulator f or testing. additional proto- type area is a v ailab le f or the user to b uild some addi- tional hardw are and connect it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , a potentiometer f or sim ulated analog input, push-b utton s witches and eight leds connected to por tb . 11.8 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii pro- g r ammer or picst ar t -plus , and easily test r mw are . the mplab-ice em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding addi- tional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 inter- f ace , push-b utton s witches , a potentiometer f or sim u- lated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connec- tion to an lcd module and a k e ypad. 11.9 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstr ation board that suppor ts the pic16c923 and pic16c924 in the plcc pac kage . it will also suppor t future 44-pin plcc microcontrollers with a lcd module . all the neces- sar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can pro- g r am the sample microcontrollers pro vided with the picdem-3 board, on a pr o ma te ii prog r am- mer or picst ar t plus with an adapter soc k et, and easily test r mw are . the mplab-ice em ulator ma y also be used with the picdem-3 board to test r m- w are . additional prototype area has been pro vided to the user f or adding hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , push-b utton s witches , a potenti- ometer f or sim ulated analog input, a ther mistor and separ ate headers f or connection to an e xter nal lcd module and a k e ypad. also pro vided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments , that is capab le of displa ying time , temper ature and da y of the w eek. the picdem-3 pro vides an addi- tional rs-232 interf ace and windo ws 3.1 softw are f or sho wing the dem ultiple x ed lcd signals on a pc . a sim- ple ser ial interf ace allo ws the user to constr uct a hard- w are dem ultiple x er f or the lcd signals .
1998 microchip technology inc. preliminary ds30235g -page 75 pic16c62x 11.10 mplab integrated de velopment en vir onment software the mplab ide softw are br ings an ease of softw are de v elopment pre viously unseen in the 8-bit microcon- troller mar k et. mplab is a windo ws based application which contains: a full f eatured editor three oper ating modes - editor - em ulator - sim ulator a project manager customizab le tool bar and k e y mapping a status bar with project inf or mation extensiv e on-line help mplab allo ws y ou to: edit y our source les (either assemb ly or ?? one touch assemb le (or compile) and do wnload to picmicro tools (automatically updates all project inf or mation) deb ug using: - source les - absolute listing le the ability to use mplab with microchip s sim ulator allo ws a consistent platf or m and the ability to easily s witch from the lo w cost sim ulator to the full f eatured em ulator with minimal retr aining due to de v elopment tools . 11.11 assemb ler (mp asm) the mp asm univ ersal macro assemb ler is a pc- hosted symbolic assemb ler . it suppor ts all microcon- troller ser ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx f amilies . mp asm off ers full f eatured macro capabilities , condi- tional assemb ly , and se v er al source and listing f or mats . it gener ates v ar ious object code f or mats to suppor t microchip's de v elopment tools as w ell as third par ty prog r ammers . mp asm allo ws full symbolic deb ugging from mplab- ice, microchip s univ ersal em ulator system. mp asm has the f ollo wing f eatures to assist in de v elop- ing softw are f or speci c use applications . pro vides tr anslation of assemb ler source code to object code f or all microchip microcontrollers . macro assemb ly capability . produces all the les (object, listing, symbol, and special) required f or symbolic deb ug with microchip s em ulator systems . suppor ts he x (def ault), decimal and octal source and listing f or mats . mp asm pro vides a r ich directiv e language to suppor t prog r amming of the picmicro . directiv es are helpful in making the de v elopment of y our assemb le source code shor ter and more maintainab le . 11.12 software sim ulator (mplab-sim) the mplab-sim softw are sim ulator allo ws code de v elopment in a pc host en vironment. it allo ws the user to sim ulate the picmicro ser ies microcontrollers on an instr uction le v el. on an y giv en instr uction, the user ma y e xamine or modify an y of the data areas or pro vide e xter nal stim ulus to an y of the pins . the input/ output r adix can be set b y the user and the e x ecution can be perf or med in; single step , e x ecute until break, or in a tr ace mode . mplab-sim fully suppor ts symbolic deb ugging using mplab-c17 and mp asm. the softw are sim ulator off ers the lo w cost e xibility to de v elop and deb ug code outside of the labor ator y en vironment making it an e xcellent m ulti-project softw are de v elopment tool. 11.13 mplab-c17 compiler the mplab-c17 code de v elopment system is a complete ansi ? compiler and integ r ated de v elop- ment en vironment f or microchip s pic17cxxx f amily of microcontrollers . the compiler pro vides po w erful inte- g r ation capabilities and ease of use not f ound with other compilers . f or easier source le v el deb ugging, the compiler pro- vides symbol inf or mation that is compatib le with the mplab ide memor y displa y . 11.14 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic de v elopment tool is a v ail- ab le in tw o v ersions - a lo w cost introductor y v ersion, mp explorer , f or designers to gain a comprehensiv e w or king kno wledge of fuzzy logic system design; and a full-f eatured v ersion, fuzzy tech-mp , edition f or imple- menting more comple x systems . both v ersions include microchip s fuzzy lab ? demon- str ation board f or hands-on e xper ience with fuzzy logic systems implementation. 11.15 seev al a ev aluation and pr ogramming system the seev al seepr om designer s kit suppor ts all microchip 2-wire and 3-wire ser ial eepr oms . the kit includes e v er ything necessar y to read, wr ite , er ase or prog r am special f eatures of an y microchip seepr om product including smar t ser ials ? and secure ser ials . the t otal endur ance ? disk is included to aid in tr ade- off analysis and reliability calculations . the total kit can signi cantly reduce time-to-mar k et and result in an optimiz ed system.
pic16c62x ds30235g -page 76 preliminary 1998 microchip technology inc. 11.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq e v aluation and prog r amming tools suppor t microchips hcs secure data products . the hcs e v al- uation kit includes an lcd displa y to sho w changing codes , a decoder to decode tr ansmissions , and a pro- g r amming interf ace to prog r am test tr ansmitters .
1998 microchip technology inc. preliminary ds30235g -page 77 pic16c62x t ab le 11-1: de velopment t ools fr om micr oc hip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model pr ogrammer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq evaluation kit k ee l oq transponder kit
pic16c62x ds30235g -page 78 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds30235g -page 79 pic16c62x 12.0 89electrical specifications absolute maxim um ratings ? ambient t emper ature under bias .............................................................................................................. -4 0 to +125 c stor age t emper ature ............................................................................................................................... .. - 65 to +150 c v oltage on an y pin with respect to v ss (e xcept v dd and mclr ) ....................................................... - 0.6v to v dd +0.6v v oltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v v oltage on mclr with respect to v ss (note 2) .................................................................................................. 0 to +14v t otal po w er dissipation (note 1) ............................................................................................................................... 1.0w maxim um current out of v ss pin ........................................................................................................................... 300 ma maxim um current into v dd pin ............................................................................................................................. 250 ma input clamp current, i ik ( v i <0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o <0 or v o > v dd ) ............................................................................................................... 20 ma maxim um output current sunk b y an y i/o pin ........................................................................................................ 25 ma maxim um output current sourced b y an y i/o pin ................................................................................................... 25 ma maxim um current sunk b y por t a and por tb ................................................................................................... 200 ma maxim um current sourced b y por t a and por tb .............................................................................................. 200 ma note 1: p o w er dissipation is calculated as f ollo ws: p dis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ) ? no tice : stresses abo v e those listed under "absolute maxim um ratings" ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . note: v oltage spik es belo w v ss at the mclr pin, inducing currents g reater than 80 ma, ma y cause latch-up . thus , a ser ies resistor of 50-100 w should be used when applying a "lo w" le v el to the mclr pin r ather than pulling this pin directly to v ss . note: v oltage spik es belo w v ss at the mclr pin, inducing currents g reater than 80 ma, ma y cause latch-up . thus , a ser ies resistor of 50-100 w should be used when applying a "lo w" le v el to the mclr pin r ather than pulling this pin directly to v ss .
pic16c62x ds30235g -page 80 preliminary 1998 microchip technology inc. t able 12-1: cr oss ref erence of de vice specs f or oscillator configurations and frequencies of operation (commer cial de vices) osc pic16c62x-04 pic16c62x a-04 pic16c62x-20 pic16c62x a- 20 pic16lc62x-04 pic16c62x/jw pic16c62xa/jw rc v dd : 3. 0v to 6.0v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. v dd : 3. 0v to 5.5v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 1.8 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 4.0 mh z max. v dd : 3.0v to 5.5v i dd : 1.8 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ . @ 3.0v i pd : 0.7 m a typ . @ 3.0v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z ma x. v dd : 3.0v to 5.5v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z ma x. xt v dd : 3. 0v to 6.0v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. v dd : 3. 0v to 5.5v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 1.8 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 4.0 mh z max. v dd : 3.0v to 5.5v i dd : 1.8 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ . @ 3.0v i pd : 0.7 m a typ . @ 3.0v f req: 4.0 mh z max. v dd : 3.0v to 6.0v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. v dd : 3.0v to 5.5v i dd : 3.3 ma max. @ 5.5v i pd : 20 m a max. @ 4.0v f req: 4.0 mh z max. hs v dd : 4.5v to 5.5v i dd : 9.0 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.0v f req: 4.0 mh z max. v dd : 4.5v to 5.5v i dd : 3.5 ma typ . @ 5.5v i pd : 1.0 m a typ . @ 4.0v f req: 4.0 mh z max. v dd : 4.5v to 5.5v i dd : 20 ma max. @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 20 mh z max. v dd : 4.5v to 5.5v i dd : 7.5 ma max. @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 20 mh z max. n/a v dd : 4.5v to 5.5v i dd : 20 ma max. @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 20 mh z max. v dd : 4.5v to 5.5v i dd : 20 ma max. @ 5.5v i pd : 1.0 m a typ . @ 4.5v f req: 20 mh z max. lp v dd : 3 .0v to 6.0v i dd : 35 m a typ . @32 khz, 3.0v i pd : 1.0 m a typ . @4.0 v f req: 200 kh z max . v dd : 3. 0v to 5.5v i dd : 35 m a typ . @32 khz, 3.0v i pd : 1.0 m a typ . @4.0 v f req: 200 kh z max . n/a n/a v dd : 2.5v to 6.0v i dd : 32 m a max . @32 khz, 3.0v i pd : 9.0 m a max . @3.0v f req: 200 kh z max. v dd : 2.5v to 6.0v i dd : 32 m a max . @32 khz, 3.0v i pd : 9.0 m a max . @3.0v f req: 200 kh z max. v dd : 3.0v to 5.5v i dd : 32 m a max . @32 khz, 3.0v i pd : 9.0 m a max . @3.0v f req: 200 kh z max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recom- mended that the user select the de vice type that the speci cations required.
1998 microchip technology inc. preliminary ds30235g -page 81 pic16c62x 12.1 dc chara cteristics: pic16c62x-04 (commer cial, industrial, extended) pic16c62x-20 (commer cial, industrial, extended) s tandar d operating conditions (unless otherwise stated) oper ating temper ature ?0 c t a +85 c f or industr ial and 0 c t a +70 c f or commercial and ?0 c t a +125 c f or e xtended p aram no. sym characteristic min t yp? max units conditions d001 d001a vdd supply v oltage 3.0 4.5 - - 6.0 5.5 v v xt , rc and lp osc con gur ation hs osc con gur ation d002 vdr ram data retention v oltage (note 1) 1.5* v de vice in sleep mode d003 vpor v dd star t v oltage to ensure p o w er-on reset vss v see section on po w er-on reset f or details d004 svdd v dd r ise r ate to ensure p o w er-on reset 0.05* v/ms see section on po w er-on reset f or details d005 v bor bro wn-out detect v oltage 3.7 3.7 4.0 4.0 4.3 4.4 v boren con gur ation bit is cleared (extended) d010 d010a d013 idd supply current (note 2) 1.8 35 9.0 3.3 70 20 ma m a ma xt and rc osc con gur ation f osc = 4 mhz, v dd = 5.5v , wdt dis- ab led (note 4) lp osc con gur ation, pic16c62x-04 only f osc = 32 khz, v dd = 4.0v , wdt dis- ab led hs osc con gur ation f osc = 20 mhz, v dd = 5.5v , wdt dis- ab led d020 ipd p o w er do wn current (note 3) 1.0 2.5 15 m a m a v dd =4.0v , wdt disab led (125 c) d023 d i wdt d i bor d i comp d i vref wdt current (note 5) bro wn-out reset current (note 5) compar ator current f or each com- par ator (note 5) v ref current (note 5) 6.0 350 20 25 425 100 300 m a m a m a m a m a v dd =4.0v (125 c) bor enab led, v dd = 5.0v v dd = 4.0v v dd = 4.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c , unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current con- sumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr i-stated, pulled to v dd , mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in k w . 5: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
pic16c62x ds30235g -page 82 preliminary 1998 microchip technology inc. 12.2 dc chara cteristics: pic16lc62x-04 (commer cial, industrial) standar d operating conditions (unless otherwise stated ) oper ating temper ature ?0?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial and ?0?c t a +125?c f or e xtended oper ating v oltage v dd r ange as descr ibed in dc spec t ab le 12-1 and t ab le 12-2 p aram no. sym characteristic min t yp? max units conditions d001 v dd supply v oltage 3.0 2.5 - 6.0 6.0 v xt and rc osc con gur ation lp osc con gur ation d002 v dr ram data retention v oltage (note 1) 1.5* v de vice in sleep mode d003 v por v dd star t v oltage to ensure p o w er-on reset v ss v see section on p o w er-on reset f or details d004 s vdd v dd r ise r ate to ensure p o w er-on reset 0.05* v/ms see section on p o w er-on reset f or details d005 v bor bro wn-out detect v oltage 3.7 4.0 4.3 v boren con gur ation bit is cleared d010 d010a i dd supply current (note 2) 1.4 26 2.5 53 ma m a xt and rc osc con gur ation f osc = 2.0 mhz, v dd = 3.0v , wdt dis- ab led (note 4) lp osc con gur ation f osc = 32 khz, v dd = 3.0v , wdt dis- ab led d020 i pd p o w er do wn current (note 3) 0.7 2 m a v dd =3.0v , wdt disab led d023 d i wdt d i bor d i comp d i vref wdt current (note 5) bro wn-out reset current (note 5) compar ator current f or each compar ator (note 5) v ref current (note 5) 6.0 350 15 425 100 300 m a m a m a m a v dd =3.0v bor enab led, v dd = 5.0v v dd = 3.0v v dd = 3.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c , unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current con- sumption. the test conditions f or all idd measurements in activ e oper ation mode are: osc1=e xter nal square w a v e , from r ail to r ail; all i/o pins tr istated, pulled to v dd , mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd to v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in k w . 5: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
1998 microchip technology inc. preliminary ds30235g -page 83 pic16c62x 12.3 dc chara cteristics: pic16c62xa/cr62xa-04 (commer cial, industrial, extended) pic16c62xa/cr62xa-20 (commer cial, industrial, extended) pic16lc62xa/lcr62xa-04 (commer cial, industrial) pic16lc62xa/lcr62xa-20 (commer cial, industrial) s tandar d operating conditions (unless otherwise stated) oper ating temper ature ?0 c t a +85 c f or industr ial and 0 c t a +70 c f or commercial and ?0 c t a +125 c f or e xtended p aram no. sym characteristic min t yp? max units conditions d001 d001a v dd supply v oltage 3.0 4.5 - - 5.5 5.5 v v xt , rc and lp osc con gur ation hs osc con gur ation d002 v dr ram data retention v oltage (note 1) 1.5* v de vice in sleep mode d003 v por v dd star t v oltage to ensure p o w er-on reset v ss v see section on po w er-on reset f or details d004 s vdd v dd r ise r ate to ensure p o w er-on reset 0.05* v/ms see section on po w er-on reset f or details d005 v bor bro wn-out detect v oltage 3.7 3.7 4.0 4.0 4.3 4.4 v boren con gur ation bit is cleared (extended) d010 d010a d013 i dd supply current (note 2) 1.2 35 3.0 2.0 70 7.5 ma m a ma xt and rc osc con gur ation f osc = 4 mhz, v dd = 5.5v , wdt disab led (note 4) lp osc con gur ation, pic16c62xa-04 only f osc = 32 khz, v dd = 4.0v , wdt disab led hs osc con gur ation f osc = 20 mhz, v dd = 5.5v , wdt disab led d020 i pd p o w er do wn current (note 3) 1.0 2.5 15 m a m a v dd =4.0v , wdt disab led (125 c) d023 d i wdt d i bor d i comp d i vref wdt current (note 5) bro wn-out reset current (note 5) compar ator current f or each compar ator (note 5) v ref current (note 5) 6.0 75 60 90 10 12 150 75 200 m a m a m a m a m a v dd =4.0v (125 c) bor enab led, v dd = 5.0v v dd = 4.0v v dd = 4.0v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c , unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current con- sumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins tr i-stated, pulled to v dd , mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is measured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: f or rc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in k w . 5: the d current is the additional current consumed when this per ipher al is enab led. this current should be added to the base i dd or i pd measurement.
pic16c62x ds30235g -page 84 preliminary 1998 microchip technology inc. 12.4 dc chara cteristics: pic 16c62x/ c62x a/cr62xa (commer cial, industrial, extended) pic 16lc62x/ lc62 xa/lcr62xa (commer cial, industrial ) standar d operating conditions (unless otherwise stated) oper ating temper ature ?0?c t a +85?c f or industr ial and 0?c t a +70?c f or commercial and ?0?c t a +125?c f or e xtended oper ating v oltage v dd r ange as descr ibed in dc spec t ab le 12-1 and t ab le 12-2 p aram. no. sym characteristic min t yp? max unit conditions v il input lo w v olta g e i/o por ts d030 with ttl b uff er v ss - 0.8 v 0.15 v dd v v dd = 4.5v to 5.5v otherwise d031 with schmitt t r igger input v ss 0. 2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) vss - 0.2 v dd v note1 d033 osc1 (in xt and hs) vss - 0.3 v dd v osc1 (in lp) vss - 0.6 v dd -1.0 v v ih input high v olta g e i/o por ts - d040 with ttl b uff er 2.0v .25 v dd + 0.8v - v dd v dd v v dd = 4.5v to 5.5v otherwise d041 with schmitt t r igger input 0.8v dd v dd d042 mclr ra4/t0cki 0.8 v dd - v dd v d043 d043a osc1 (xt , hs and lp) osc1 (in rc mode) 0.7 v dd 0. 9v dd - v dd v note1 d070 i purb p or tb w eak pull-up current 50 200 400 m a v dd = 5.0v , v pin = v ss i il input leaka g e current (notes 2, 3) i/o por ts (except por t a) 1.0 m a v ss v pin v dd , pin at hi- impedance d060 por t a - - 0.5 m a vss v pin v dd , pin at hi- impedance d061 ra4/t0cki - - 1.0 m a vss v pin v dd d063 osc1, mclr - - 5.0 m a vss v pin v dd , xt , hs and lp osc con gur ation v ol output lo w v olta g e d080 i/o por ts - - 0.6 v i ol =8.5 ma, v dd =4.5v , -40 to +85 c - - 0.6 v i ol =7.0 ma, v dd =4.5v , +125 c d083 osc2/clk out (rc only) - - 0.6 v i ol =1.6 ma, v dd =4.5v , -40 to +85 c - - 0.6 v i ol =1.2 ma, v dd =4.5v , +125 c v oh output high v olta g e (note 3) d090 i/o por ts (except ra4) v dd -0.7 - - v i oh =-3.0 ma, v dd =4.5v , -40 to +85 c v dd -0.7 - - v i oh =-2.5 ma, v dd =4.5v , +125 c d092 osc2/clk out (rc only) v dd -0.7 - - v i oh =-1.3 ma, v dd =4.5v , -40 to +85 c v dd -0.7 - - v i oh =-1.0 ma, v dd =4.5v , +125 c * v od open-drain high v olta g e 10* 10* v ra4 pin pic16c62x, pic16lc62x ra4 pin pic16c62xa, piclc62xa, cr62xa, lcr62xa capacitive loading specs on output pins d100 c osc2 osc2 pin 15 pf in xt , hs and lp modes when e xter nal cloc k used to dr iv e osc1. d101 cio all i/o pins/osc2 (in rc mode) 50 pf * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5.0v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in rc oscillator con gur ation, the osc1 pin is a schmitt t r igger input. it is not recommended that the pic16c62x(a) be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on applied v oltage le v el. the speci ed le v els represent nor mal oper at- ing conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin.
1998 microchip technology inc. preliminary ds30235g -page 85 pic16c62x t able 12-2: comparator specifications oper ating conditions: vdd r ange as descr ibed in t ab le 12-1, -40 c tr ansitions from 0000 to 1111 .
pic16c62x ds30235g -page 86 preliminary 1998 microchip technology inc. 12.5 timing p arameter symbology the timing par ameter symbols ha v e been created with one of the f ollo wing f or mats: figure 12-1: load conditions 1. tpps2pps 2. tpps t f f requency t time lo w ercase subscr ipts (pp) and their meanings: pp c k clk out osc osc1 io i/o por t t0 t0cki mc mclr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l l o w z hi - imped a nce v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 output load condition 1 load condition 2
1998 microchip technology inc. preliminary ds30235g -page 87 pic16c62x 12.6 timing dia grams and speci cations figure 12-2: external cloc k timing t able 12-4: external cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f os external clkin frequenc y (note 1) dc 4 mhz xt and rc osc mode , v dd =5.0v dc 20 mhz hs osc mode dc 200 khz lp osc mode oscillator frequenc y (note 1) dc 4 mhz rc osc mode , v dd =5.0v 0.1 4 mhz xt osc mode 1 20 mhz hs osc mode dc 200 khz lp osc mode 1 t osc external clkin p eriod (note 1) 250 ns xt and rc osc mode 50 ns hs osc mode 5 m s lp osc mode oscillator p eriod (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 50 1,000 ns hs osc mode 5 m s lp osc mode 2 t cy instruction cyc le time (note 1) 1.0 f osc/4 dc m s t cys = f osc /4 3 * t osl, t osh exter nal cloc k in (osc1) high or lo w time 100* ns xt oscillator , t osc l/h duty cycle 2* m s lp oscillator , t osc l/h duty cycle 20* ns hs oscillator , t osc l/h duty cycle 4 * t osr, t osf exter nal cloc k in (osc1) rise or f all time 25 * ns xt oscillator 50 * ns lp oscillator 15 * ns hs oscillator * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time - base per iod. all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. all de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1 pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices . osc1 clk out q4 q1 q2 q3 q4 q1 1 3 3 4 4 2
pic16c62x ds30235g -page 88 preliminary 1998 microchip technology inc. figure 12-3: clk out and i/o timing 22 23 note: all tests m ust be do with speci ed capacitance loads ( figure 12-1 ) 50 pf on i/o pins and clk out osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
1998 microchip technology inc. preliminary ds30235g -page 89 pic16c62x t able 12-5: clk out and i/o timing requirements p arameter # sym characteristic min t yp? max units conditions 10 * t osh2c kl osc1 - to clk out (1) 75 200 400 n s ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 11 * t osh2c kh osc1 - to clk out - (1) 75 200 400 n s ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 12 * tc kr clk out r ise time (1) 35 100 200 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 13 * tc kf clk out f all time (1) 35 100 200 n s ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 14 * tc kl2iov clk out to p or t out v alid (1) 20 ns 15 * tiov2c kh p or t in v alid bef ore clk out - (1) t osc +200 ns t osc +400 ns ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 16 * tc kh2ioi p or t in hold after clk out - (1) 0 ns 17 * t osh2iov osc1 - (q1 cycle) to p or t out v alid 50 150 300 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 18 * t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) 100 200 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 19 * tiov2osh p or t input v alid to osc1 - (i/o in setup time) 0 n s 20 * tior p or t output r ise time 10 40 80 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 21 * tiof p or t output f all time 10 40 80 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 22 * tinp rb0/int pin high or lo w time 25 40 ns ns pic16c62x (a) pic16lc62x (a) pic16cr62xa pic16lcr62xa 23 t rbp rb<7:4> change interr upt high or lo w time t cy n s * these par ameters are char acter iz ed b ut not tested ? data in "t yp" column is at 5.0v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: measurements are tak en in rc mode where clk out output is 4 x t osc
pic16c62x ds30235g -page 90 preliminary 1998 microchip technology inc. figure 12-4: reset, w atc hdog timer , oscillator star t-up timer and p o wer -up timer timing figure 12-5: br o wn-out reset timing t able 12-6: reset, w atc hdog timer , oscillator star t-up timer and p o wer -up timer requirements p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 2000 ns - 40 to +85 c 31 t wdt w atchdog timer time-out p er iod (no prescaler) 7* 18 33* ms v dd = 5.0v , -40 to +85 c 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33 tpwr t p o w er-up timer p er iod 28* 72 132* ms v dd = 5.0v , -40 to +85 c 34 t ioz i/o hi-impedance from mclr lo w 2. 0 m s 35 t bor bro wn-out reset pulse width 100 * m s 3.7v v dd 4.3v * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t timeout osc timeout inter nal reset w atchdog timer reset 33 32 30 31 3 4 i/o pins 3 4 v dd bv dd 35
1998 microchip technology inc. preliminary ds30235g -page 91 pic16c62x figure 12-6: timer0 cloc k timing t able 12-7: timer0 cloc k requirements figure 12-7: load conditions p arameter no. sym characteristic min t yp? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki p er iod t cy + 40 * n ns n = prescale v alue (1, 2, 4, ..., 256) * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5.0v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 41 42 40 ra4/t0cki tmr0 v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 output load condition 1 load condition 2
pic16c62x ds30235g -page 92 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds30235g -page 93 pic16c62x 13.0 de vice characterization inf ormation not a v ailab le at this time .
pic16c62x ds30235g -page 94 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds30235g -page 95 pic16c62x 14.0 p ac ka ging inf ormation p ac ka g e t ype: k04-010 18-lead ceramic dual in-line with windo w (jw) ?300 mil * controlling p ar ameter . n 2 1 r min windo w length windo w width ov er all ro w spacing radius to radius width p ac kage width p ac kage length tip to seating plane base to seating plane t op of lead to seating plane t op to seating plane lead thic kness shoulder radius upper lead width lo w er lead width number of pins pcb ro w spacing dimension limits pitch units eb w2 w1 l e e1 d a1 a2 a b c r b1 n p 0.15 7.24 7.87 0.76 3.33 4.83 0.30 0.38 1.52 0.53 2.59 0.200 0.140 0.385 0.270 0.298 0.900 0.138 0.023 0.111 0.183 0.190 0.130 0.345 0.125 0.255 0.285 0.880 0.015 0.091 0.175 0.210 0.150 0.425 0.150 0.285 0.310 0.920 0.030 0.131 0.190 0.010 0.013 0.055 0.019 0.100 0.300 nom 0.016 0.008 0.010 0.050 0.098 inches* max 18 0.021 0.012 0.015 0.060 0.102 22.86 0.19 0.13 8.76 6.48 7.24 22.35 3.18 0.00 2.31 4.45 0.2 0.14 9.78 10.80 0.21 3.49 6.86 7.56 0.57 2.82 4.64 3.81 23.37 nom millimeters min 0.20 0.25 1.27 0.41 2.49 max 0.47 0.25 0.32 1.40 2.54 18 7.62 d w2 e w1 c eb e1 p l a1 b b1 a a2
pic16c62x ds30235g -page 96 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-007 18-lead plastic dual in-line (p) ?300 mil * controlling p ar ameter . ? dimension ?1 does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. units inches* millimeters dimension limits min nom max min nom max pcb ro w spacing 0.300 7.62 number of pins n 18 18 pitch p 0.100 2.54 lo w er lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thic kness c 0.005 0.010 0.015 0.13 0.25 0.38 t op to seating plane a 0.110 0.155 0.155 2.79 3.94 3.94 t op of lead to seating plane a1 0.075 0.095 0.115 1.91 2.41 2.92 base to seating plane a2 0.000 0.020 0.020 0.00 0.51 0.51 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 p ac kage length d 0.890 0.895 0.900 22.61 22.73 22.86 molded p ac kage width e 0.245 0.255 0.265 6.22 6.48 6.73 radius to radius width e1 0.230 0.250 0.270 5.84 6.35 6.86 ov er all ro w spacing eb 0.310 0.349 0.387 7.87 8.85 9.83 mold dr aft angle t op a 5 10 15 5 10 15 mold dr aft angle bottom b 5 10 15 5 10 15 r n 2 1 d e c eb b e1 a p a1 l b1 b a a2
1998 microchip technology inc. preliminary ds30235g -page 97 pic16c62x p ac ka g e t ype: k04-051 18-lead plastic small outline (so) ? wide , 300 mil 0.014 0.009 0.010 0.011 0.005 0.005 0.010 0.394 0.292 0.450 0.004 0.048 0.093 min n number of pins mold dr aft angle bottom mold dr aft angle t op lo w er lead width chamf er distance outside dimension molded p ac kage width molded p ac kage length ov er all p ac k. height lead thic kness radius center line f oot angle f oot length gull wing radius shoulder radius standoff shoulder height b a r2 r1 e1 a2 a1 x f b ? c l1 l e d a dimension limits pitch units p 18 18 0 0 12 12 15 15 4 0.020 0 0.017 0.011 0.015 0.016 0.005 0.005 0.407 0.296 0.456 0.008 0.058 0.099 0.029 0.019 0.012 0.020 0.021 0.010 0.010 8 0.419 0.299 0.462 0.011 0.068 0.104 0 0 12 12 15 15 0.42 0.27 0.38 0.41 0.13 0.13 0.50 10.33 7.51 11.58 0.19 1.47 2.50 0.25 0 0.36 0.23 0.25 0.28 0.13 0.13 10.01 7.42 11.43 0.10 1.22 2.36 0.74 4 8 0.48 0.30 0.51 0.53 0.25 0.25 10.64 7.59 11.73 0.28 1.73 2.64 inches* 0.050 nom max 1.27 millimeters min nom max n 2 1 r2 r1 l1 l b c f x 45 d p b e e1 a a1 a2 a * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c62x ds30235g -page 98 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-072 20-lead plastic shrink small outine (ss) ?5.30 mm min p pitch mold dr aft angle bottom mold dr aft angle t op lo w er lead width radius center line gull wing radius shoulder radius outside dimension molded p ac kage width molded p ac kage length shoulder height ov er all p ac k. height lead thic kness f oot angle f oot length standoff number of pins b a c f a2 a1 a n e1 b ? l1 r2 l r1 e d dimension limits units 0.65 0.026 8 0 0 5 5 10 10 0.012 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.283 0.005 0.036 0.073 20 0.301 0 0.010 0.005 0.000 0.015 0.005 0.005 0.205 0.278 0.002 0.026 0.068 0.311 0.015 0.009 0.010 0.025 0.010 0.010 4 8 0.212 0.289 0.008 0.046 0.078 0 0 5 5 10 10 7.65 0.25 0.13 0.00 0.38 0.13 0.13 0 5.20 7.07 0.05 0.66 1.73 7.90 7.78 4 0.32 0.18 0.13 0.13 0.51 0.13 0.38 0.22 0.25 0.25 0.64 0.25 5.29 7.20 0.13 20 1.86 0.91 5.38 7.33 0.21 1.99 1.17 nom inches max nom millimeters* min max n 1 2 r1 r2 d p b e1 e l1 l c b f a a1 a a2 * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
1998 microchip technology inc. preliminary ds30235g -page 99 pic16c62x 14.1 p ac ka g e m arking inf ormation 20-lead ssop xxxxxxx xxx aabbcde xxxxxxx xxx xxxxxxxx xxxxxxxx aabbcde 18-lead cerdip windo wed 18-lead soic (.300") xxxxxxx xxxxx aabbcde xxxxxxx xxxxx xxxxxxx xxxxx x xxxxxxxxx xxxxxxx xxxxxxxxx xxxxxxx x aabbcde 18-lead pdip example -04i / 218 9 8 51 cbp pic16c 622a 16c 622 /jw 9 8 01 cba example example -04i / s0218 9 8 18 cdk pic16c 622 pic16c 622a -04i / p456 9 8 23 cba example leg end: mm...m microchip par t n umber inf or mation xx...x customer speci c inf or mation* aa y ear code (last 2 digits of calendar y ear) bb w eek code (w eek of j an uar y 1 is w eek ?1? c f acility code of the plant at which w af er is man uf actured o = outside v endor c = 5 line s = 6 line h = 8 line d mask re vision n umber e assemb ly code of the plant or countr y of or igin in which par t w as assemb le d note : in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. * standard o tp mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re v#, and assemb ly code . f or o tp mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . f or qtp de vices , an y special mar king adders are included in qtp pr ice .
pic16c62x ds30235g -page 100 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds30235g -page 101 pic16c62x appendix a: enhancements the f ollo wing are the list of enhancements o v er the pic16c5x microcontroller f amily: 1. instr uction w ord length is increased to 14 bits . this allo ws larger page siz es both in prog r am memor y (4k no w as opposed to 512 bef ore) and register le (up to 128 b ytes no w v ersus 32 b ytes bef ore). 2. a pc high latch register (pcla th) is added to handle prog r am memor y paging. p a2, p a1, p a0 bits are remo v ed from status register . 3. data memor y paging is slightly red e ned. st a tus register is modi ed. 4. f our ne w instr uctions ha v e been added: return , retfie , addlw , and sublw . t w o instr uctions t ris and option are being phased out although the y are k ept f or compatibility with pic16c5x. 5. option and tris registers are made addressab le . 6. interr upt capability is added. interr upt v ector is at 0004h. 7. stac k siz e is increased to 8 deep . 8. reset v ector is changed to 0000h. 9. reset of all registers is re visited. fiv e diff erent reset (and w ak e-up) types are recogniz ed. registers are reset diff erently . 10. w ak e up from sleep through interr upt is added. 11. t w o separ ate timers , oscillator star t-up timer (ost) and p o w er-up timer (pwr t) are included f or more reliab le po w er-up . these timers are in v ok ed selectiv ely to a v oid unnecessar y dela ys on po w er-up and w ak e-up . 12. p or tb has w eak pull-ups and interr upt on change f eature . 13. time r 0 cloc k input, t0cki pin is also a por t pin (ra4/t 0 cki) and has a tris bit. 14. fsr is made a full 8-bit register . 15. ?n-circuit prog r amming is made possib le . the user can prog r am pic16cxx de vices using only v e pins: v dd , v ss , /v pp , rb6 (cloc k) and rb7 (data in/out). 16. pcon status register is added with a p o w er-on-reset ( por ) status bit and a bro wn-out reset status bit ( bor ). 17. code protection scheme is enhanced such that por tions of the prog r am memor y can be protected, while the remainder is unprotected. 18. por t a inputs a re no w schmitt t r igger inputs . 19. bro wn-out reset reset has been added. 20. common ram registers f0h-ffh implemented in bank1. appendix b: compatibility t o con v er t code wr itten f or pic16c5x to pic16cxx, the user should tak e the f ollo wing steps: 1. remo v e an y prog r am memor y page select oper ations (p a2, p a1, p a0 bits) f or call , goto . 2. re visit an y computed jump oper ations (wr ite to pc or add to pc , etc.) to mak e sure page bits are set proper ly under the ne w scheme . 3. eliminate an y data memor y page s witching. rede ne data v ar iab les to reallocate them. 4. v er ify all wr ites to st a tus , option, and fsr registers since these ha v e changed. 5. change reset v ector to 0000h.
pic16c62x ds30235g -page 102 preliminary 1998 microchip technology inc. appendix c: what s ne w the f or mat of cer tain sections of this data sheet ha v e been changed to be consistent with other product f amilies . 1. por tb in put b uff ers ha v e changed to ttl from schmitt t r igger . appendix d: what s chang ed 1. t ab le 3-1 w as changed to re ect the ttl input b uff ers on por tb . 2. figure 5-5 and figure 5-6 w ere updated to re ect the ttl input b uff ers on por tb . 3. figure 9-7 w as updated. 4. the or ientation of the diode in figure 9-19 w as changed. 5. a de vice speci cation f or jw de vices w as added to t ab le 12-1 . 6. max spec f or bro wn-out reset current w as changed to 15 m a in section 12.1 and section 12.2 . 7. inf or mation added to suppor t the 2.5v "lc" de vices . 8. inf or mation added to suppor t the "a" v ersion of the de vices .
1998 microchip technology inc. preliminary ds30235g -page 103 pic16c62x inde x a addlw instruction ............................................................. 63 addwf instruction ............................................................. 63 andlw instruction ............................................................. 63 andwf instruction ............................................................. 63 architectural overview .......................................................... 9 assembler mpasm assembler ..................................................... 75 b bcf instruction ................................................................... 64 block diagram timer0 ....................................................................... 31 tmr0/wdt prescaler .......................................... 34 brown-out detect (bod) .................................................... 50 bsf instruction ................................................................... 64 btfsc instruction ............................................................... 64 btfss instruction ............................................................... 65 c call instruction ................................................................. 65 clocking scheme/instruction cycle .................................... 12 clrf instruction ................................................................. 65 clrw instruction ................................................................ 65 clrwdt instruction ........................................................... 66 cmcon register ................................................................ 37 code protection .................................................................. 60 comf instruction ................................................................ 66 comparator configuration ................................................... 38 comparator interrupts ......................................................... 41 comparator module ............................................................ 37 comparator operation ........................................................ 39 comparator reference ....................................................... 39 configuration bits ................................................................ 46 configuring the voltage reference ..................................... 43 crystal operation ................................................................ 47 d data memory organization ................................................. 14 decf instruction ................................................................. 66 decfsz instruction ............................................................ 66 development support ......................................................... 73 development tools ............................................................. 73 e errata .................................................................................... 3 external crystal oscillator circuit ....................................... 48 f fuzzy logic dev. system ( fuzzy tech -mp) .................... 75 g general purpose register file ............................................ 14 goto instruction ................................................................ 67 i i/o ports .............................................................................. 25 i/o programming considerations ........................................ 30 icepic low-cost pic16cxxx in-circuit emulator ............ 73 id locations ........................................................................ 60 incf instruction .................................................................. 67 incfsz instruction ............................................................. 67 in-circuit serial programming ............................................. 60 indirect addressing, indf and fsr registers ................... 24 instruction flow/pipelining .................................................. 12 instruction set addlw ....................................................................... 63 addwf ...................................................................... 63 andlw ....................................................................... 63 andwf ...................................................................... 63 bcf ............................................................................ 64 bsf ............................................................................. 64 btfsc ........................................................................ 64 btfss ........................................................................ 65 call ........................................................................... 65 clrf .......................................................................... 65 clrw ......................................................................... 65 clrwdt .................................................................... 66 comf ......................................................................... 66 decf .......................................................................... 66 decfsz ..................................................................... 66 goto ......................................................................... 67 incf ........................................................................... 67 incfsz ....................................................................... 67 iorlw ........................................................................ 67 iorwf ........................................................................ 68 movf ......................................................................... 68 movlw ...................................................................... 68 movwf ...................................................................... 68 nop ............................................................................ 69 option ...................................................................... 69 retfie ....................................................................... 69 retlw ....................................................................... 69 return ..................................................................... 70 rlf ............................................................................. 70 rrf ............................................................................ 70 sleep ........................................................................ 70 sublw ....................................................................... 71 subwf ....................................................................... 71 swapf ....................................................................... 72 tris ........................................................................... 72 xorlw ...................................................................... 72 xorwf ...................................................................... 72 instruction set summary .................................................... 61 int interrupt ....................................................................... 56 intcon register ............................................................... 20 interrupts ............................................................................ 55 iorlw instruction .............................................................. 67 iorwf instruction .............................................................. 68 k keeloq evaluation and programming tools ................... 76 m movf instruction ................................................................ 68 movlw instruction ............................................................ 68 movwf instruction ............................................................ 68 mplab integrated development environment software ............................................................................. 75 n nop instruction .................................................................. 69 o one-time-programmable (otp) devices ............................. 7 option instruction ............................................................ 69 option register ............................................................... 19 oscillator configurations .................................................... 47 oscillator start-up timer (ost) .......................................... 50
pic16c62x ds30235g -page 104 preliminary 1998 microchip technology inc. p package marking information ............................................. 99 packaging information ........................................................ 95 pcl and pclath ............................................................... 23 pcon register ................................................................... 22 picdem-1 low-cost picmicro demo board ...................... 74 picdem-2 low-cost pic16cxx demo board ................... 74 picdem-3 low-cost pic16cxxx demo board ................. 74 picstart plus entry level development system ......... 73 pie1 register ...................................................................... 21 pinout description ............................................................... 11 pir1 register ...................................................................... 21 port rb interrupt ................................................................. 56 porta ................................................................................ 25 portb ................................................................................ 28 power control/status register (pcon) .............................. 51 power-down mode (sleep) ............................................... 59 power-on reset (por) ...................................................... 50 power-up timer (pwrt) ..................................................... 50 prescaler ............................................................................. 34 pro mate ii universal programmer ............................... 73 program memory organization ........................................... 13 q quick-turnaround-production (qtp) devices ...................... 7 r rc oscillator ....................................................................... 48 reset ................................................................................... 49 retfie instruction .............................................................. 69 retlw instruction .............................................................. 69 return instruction ............................................................ 70 rlf instruction .................................................................... 70 rrf instruction ................................................................... 70 s seeval evaluation and programming system ............... 75 serialized quick-turnaround-production (sqtp) devices .................................................................... 7 sleep instruction ............................................................... 70 software simulator (mplab-sim) ....................................... 75 special features of the cpu ............................................... 45 special function registers ................................................. 17 stack ................................................................................... 23 status register .................................................................... 18 sublw instruction .............................................................. 71 subwf instruction .............................................................. 71 swapf instruction .............................................................. 72 t timer0 timer0 ....................................................................... 31 timer0 (tmr0) interrupt ........................................... 31 timer0 (tmr0) module ............................................. 31 tmr0 with external clock ........................................... 33 timer1 switching prescaler assignment ................................. 35 timing diagrams and specifications ................................... 87 tmr0 interrupt .................................................................... 56 tris instruction .................................................................. 72 trisa .................................................................................. 25 trisb .................................................................................. 28 v voltage reference module ................................................. 43 vrcon register ................................................................ 43 w watchdog timer (wdt) ...................................................... 57 www, on-line support ....................................................... 3 x xorlw instruction ............................................................. 72 xorwf instruction ............................................................. 72
1998 microchip technology inc. ds30235g -page 105 pic16c62x systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . picmicro , fle x r om, mplab and fuzzy- lab are tr ademar ks and sqtp is a ser vice mar k of micro- chip in the u .s .a. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides on-line suppor t on the microchip w or ld wide w eb (www) site . the w eb site is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone .com/pub/micr oc hip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products conf erences f or products , de v elopment systems , technical inf or mation and more listing of seminars and e v ents 980106
pic16c62x ds30235g -page 106 1998 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds30235g pic16c62x
1998 microchip technology inc. preliminary ds30235g -page 107 pic16c62x pic16c62x pr oduct identification system t o order or to obtain inf or mation, e .g., on pr icing or deliv er y , please use the listed par t n umbers , and ref er to the f actor y or the listed sales of ces . * jw de vices are uv er asab le and can be prog r ammed to an y de vice con gur ation. jw de vices meet the electr ical requirement of each oscillator type (including lc de vices). sales and suppor t products suppor ted b y a preliminar y data sheet ma y possib ly ha v e an err ata sheet descr ibing minor oper ational diff erences and recommended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. f or latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. p attern: 3-digit p atter n code f or qtp (b lank otherwise) p ac ka g e: p = pdip so = soic (gull wing, 300 mil body) ss = ssop (209 mil) jw* = windo w ed cerdip t emperature - = 0 ? c to +70 ? c rang e: i = ?0 ? c to +85 ? c e = ?0 ? c to +125 ? c frequenc y 04 = 200khz (lp osc) rang e: 04 = 4 mhz (xt and rc osc) 20 = 20 mhz (hs osc) de vice: pic16c62x :v dd r ange 3. 0v to 6.0v pic16c62xt :v dd r ange 3. 0v to 6.0v (t ape and reel) pic16c62xa: v dd r ange 3.0v to 5.5v pic16c62xa t : v dd r ange 3.0v to 5.5v (t ape and reel) pic16lc62x :v dd r ange 2.5v to 6.0v pic16lc62xt :v dd r ange 2.5v to 6.0v (t ape and reel) pic16lc62xa :v dd r ange 2.5v to 5.5v pic16lc62xa t :v dd r ange 2.5v to 5.5v (t ape and reel) pic16cr620a: v dd r ange 2.5v to 5.5v pic16cr620a t : v dd r ange 2.5v to 5.5v (t ape and reel) pic16lcr620a: v dd r ange 2.0v to 5.5v pic16lcr620a t : vdd r ange 2.0v to 5.5v (t ape and reel) pic16cr620t : v dd r an g e 3.0v to 5.5v ( t ape and reel ) examples: g) pic16c621a - 04/p 301 = commercial temp ., pdip pac k- age , 4 mhz, nor mal v dd limits , qtp patter n #301. h) pic16lc62 2- 04i/so = industr ial temp ., soic pac k- age , 200khz, e xtended v dd limits . p ar t no . -xx x /xx xxx
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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